A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.

A lateral bipolar junction transistor (LBJT) device that includes an intrinsic III-V semiconductor material having a first band gap; and a base region present on the intrinsic III-V semiconductor material. The base region is composed of an III-V semiconductor material having a second band gap that is less than the first band gap. Emitter and collector regions present on opposing sides of the base region. The emitter and collector regions are composed of epitaxial III-V semiconductor material that is present on the intrinsic III-V semiconductor material.

A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.

Embodiments of a semiconductor device include a base substrate including an upper surface, a nucleation layer disposed over the upper surface of the base substrate, a first semiconductor layer disposed over the nucleation layer, a second semiconductor layer disposed over the first semiconductor layer, a channel within the second semiconductor layer and proximate to an upper surface of the second semiconductor layer, and an enhanced resistivity region with an upper boundary proximate to an upper surface of the first semiconductor layer. The enhanced resistivity region has an upper boundary located a distance below the channel. Embodiments of a method of fabricating the semiconductor device include implanting one or more ion species through the first semiconductor layer to form the enhanced resistivity region.

A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.

A transistor device is provided. The transistor device includes a substrate, a channel layer on the substrate, the channel layer including a GaN material, a barrier layer that is on the channel layer and that includes an AlGaN material, a drain electrode that is on the barrier layer in a drain region of the device, a source ohmic structure that is at least partially recessed into the barrier layer in a source region of the device, a source electrode that is on the source ohmic structure and a gate contact that is on the barrier layer and that is in a gate region of the device that is between the drain region and the source region.

A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.

A technique of reducing the manufacturing cost of a semiconductor device is provided, There is provided a method of manufacturing a semiconductor device comprising an ion implantation process of implanting at least one of magnesium and beryllium by ion implantation into a first semiconductor layer that is mainly formed from a group III nitride; and a heating process of heating the first semiconductor layer in an atmosphere that includes an anneal gas of at least one of magnesium and beryllium, after the ion implantation process,

A semiconductor device including a substrate, a plurality of III-nitride semiconductor layers, a source electrode, a gate electrode, a drain electrode, and a doped layer. The III-nitride semiconductor layers are disposed on the substrate. A two dimensional electron gas (2DEG) channel is formed in the III-nitride semiconductor layers. The source electrode, the gate electrode, and the drain electrode are disposed on the III-nitride semiconductor layers. The gate electrode is located between the source electrode and the drain electrode. The source electrode and the drain electrode are electrically connected to the 2DEG channel. A lateral direction is defined from the source electrode to the drain electrode. The doped layer is disposed between the gate electrode and the III-nitride semiconductor layers. The doped layer includes a plurality of dopants, and a concentration of the dopants varies along the lateral direction.