A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type impurity is provided. A method of manufacturing a semiconductor device having a trench gate structure comprises an n-type semiconductor region forming process. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which a p-type impurity contained in a p-type semiconductor layer is diffused is formed in at least part of an n-type semiconductor layer that is located below an n-type semiconductor region.

A semiconductor device includes a substrate having an upper surface layer of a second conduction type formed at an upper surface side, a drift layer of a first conduction type formed under the upper surface layer, a buffer layer of the first conduction type formed under the drift layer, and a lower surface layer of the second conduction type formed under the buffer layer, the buffer layer includes a plurality of upper buffer layers provided apart from each other, and a plurality of lower buffer layers provided apart from each other between the plurality of upper buffer layers and the lower surface layer, wherein the plurality of upper buffer layers are formed so that average impurity concentrations in first sections each extending from the upper end of one of the upper buffer layers to the next lower buffer layer are unified as a first concentration.

When a defect region is present near the pn junction in a GaN layer, lattice defects are present in the depletion layer. Therefore, when a reverse bias is applied to the pn junction, the defects in the depletion layer cause the generated current to flow as a leakage current. The leakage current flowing through the depletion layer can cause a decrease in the withstand voltage at the pn junction. Provided is a semiconductor device using gallium nitride, including a gallium nitride layer including an n-type region. The gallium nitride layer includes a first p-type well region and a second p-type well region that is provided on at least a portion of the first p-type well region and has a peak region with a higher p-type impurity concentration than the first p-type well region.

An impurity of a second conductivity type is selectively doped in a surface of a semiconductor substrate of a first conductivity type to form doped regions. A portion of a surface of the doped regions is covered by a heat insulating film. At least a remaining portion of the surface of the doped regions is covered by an absorbing film and the doped regions are heated through the absorbing film, enabling an impurity region of the second conductivity type to be formed having two or more of the doped regions that have a same impurity concentration and differing carrier concentrations.

A technique of reducing the complication in manufacture is provided. There is provided a semiconductor device comprising an n-type semiconductor region made of a nitride semiconductor containing gallium; a p-type semiconductor region arranged to be adjacent to and in contact with the n-type semiconductor region and made of the nitride semiconductor; a first electrode arranged to be in ohmic contact with the n-type semiconductor region; and a second electrode arranged to be in ohmic contact with the p-type semiconductor region. The first electrode and the second electrode are mainly made of one identical metal. The identical metal is at least one metal selected from the group consisting of palladium, nickel and platinum. A concentration of a p-type impurity in the n-type semiconductor region is approximately equal to a concentration of the p-type impurity in the p-type semiconductor region. A difference between a concentration of an n-type impurity and the concentration of the p-type impurity in the n-type semiconductor region is not less than 1.0×10.sup.19 cm.sup.−3.

To provide a semiconductor epitaxial wafer having an epitaxial layer with excellent crystallinity, the semiconductor epitaxial wafer is a semiconductor epitaxial wafer in which an epitaxial layer is formed on a surface of a semiconductor wafer, and the peak of the hydrogen concentration profile detected by SIMS lies in a surface portion of the semiconductor wafer on the side where the on the side where the epitaxial layer is formed.

A semiconductor device includes an active device region and a plurality of guard rings arranged in a first concentric pattern surrounding the active device region. The semiconductor device also includes a plurality of junctions arranged in a second concentric pattern surrounding the active device region. At least one of the plurality of junctions is arranged between two adjacent guard rings of the plurality of guard rings, and the plurality of junctions have a different resistivity than the plurality of guard rings. The semiconductor device further includes a plurality of coupling paths. At least one of the plurality of coupling paths is arranged to connect two adjacent guard rings of the plurality of guard rings.

In certain examples, methods and semiconductor structures are directed to use of a doped buried region (e.g., Mg-dopant) including a III-Nitride material and having a diffusion path (“ion diffusion path”) that includes hydrogen introduced by using ion implantation via at least one ion species. An ion implantation thermal treatment causes hydrogen to diffuse through the ion implanted path and causes activation of the buried region. In more specific examples in which such semiconductor structures have an ohmic contact region at which a source of a transistor interfaces with the buried region, the ohmic contact region is without etching-based damage due at least in part to the post-ion implantation thermal treatment.

A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 10.sup.18-10.sup.22 cm.sup.−3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N.sub.2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).

A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.