An apparatus for etching one side of a semiconductor layer of a workpiece, including at least one etching basin for receiving an electrolyte, a first electrode which is provided for electrically contacting the electrolyte located in the etching basin, a second electrode which is provided for electrically contacting the semiconductor layer, a electrical power source which is electrically conductively connected to the first and the second electrodes for generating an etching current, and a transport apparatus for transporting the workpiece relative to the etching basin such that a semiconductor layer etching face to be etched can be wetted by the electrolyte in the etching basin. The transport apparatus has a negative pressure holding element for the workpiece, designed to position the workpiece on a retaining face of the workpiece opposite to the etching face by negative pressure, and the second electrode is positioned on the negative pressure holding element such that, when the workpiece is positioned on the negative pressure holding element, the retaining face of the workpiece is contacted by the second electrode. A method for etching one side of a semiconductor layer of a workpiece is also provided.

A method includes depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately; patterning the first and second semiconductor layers to form a fin structure; supplying a first bias to the substrate after patterning the first and second semiconductor layers; and etching the second semiconductor layers when the semiconductor substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.

Structures and methods for forming highly uniform and high-porosity gallium-nitride layers with sub-100-nm pore sizes are described. Electrochemical etching of heavily-doped gallium nitride at low bias voltages in concentrated nitric acid is used to form the porous gallium nitride. The porous layers may be used in reflective structures for integrated optical devices such as VCSELs and LEDs.

A method for producing at least one pattern in a substrate is provided, including providing a substrate having a front face surmounted by at least one masking layer carrying at least one mask pattern, carrying out an ion implantation of the substrate so as to form at least one first zone having a resistivity ρ1 less than a resistivity ρ2 of at least one second non-modified zone, after the ion implantation step, immersing the substrate in an electrolyte, and removing the at least one first zone selectively at the at least one second zone, the removing including at least an application of an electrochemistry step to the substrate to cause a porosification of the at least one first zone selectively at the at least one second zone.

A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically conductive doped GaN layer locally covered with InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) connecting the electrically conductive doped GaN layer and a counter-electrode (500) to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second electrode to porosify the doped InGaN layer, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.

A substrate processing apparatus comprising: a stage for holding a substrate with a surface to be processed upward; a catalyst holding head for holding a catalyst to process the surface to be processed of the substrate; a pushing mechanism for pushing the catalyst holding head against the surface to be processed of the substrate; a swing mechanism for swinging the catalyst holding head in a radial direction of the substrate; and a pushing force control unit configured to adjust a pushing force of the catalyst holding head by the pushing mechanism according to a position of the catalyst holding head or a contact area between the substrate and the catalyst when the catalyst projects to outside the substrate by the swing of the catalyst holding head.

A method for etching a semiconductor structure (110) is provided, the semiconductor structure comprising a sub-surface quantum structure (30) of a first III-V semiconductor material,beneath a surface layer (31) of a second III-V semiconductor material having a charge carrier density of less than 510.sup.17 cm.sup.3. The sub-surface quantum structure may comprise, for example, a quantum well, or a quantum wire, or a quantum dot. The method comprises the steps of exposing the surface layer to an electrolyte (130), and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically etch the sub-surface quantum structure (30) to form a plurality of nanostructures, while the surface layer (31) is not etched. A semiconductor structure, uses thereof, and devices incorporating such semiconductor structures are further provided.

A Group III nitride semiconductor for growing a high-quality crystal having a low defect density and a method for producing the Group III nitride semiconductor. The Group III nitride semiconductor includes an RAMO.sub.4 substrate including a single crystal represented by the general formula RAMO.sub.4 (where R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn and Cd); a p-type Group III nitride crystal layer disposed on the RAMO.sub.4 substrate; a plurality of n-type Group III nitride crystal layers disposed on the p-type Group III nitride crystal layer; and a Group III nitride crystal layer disposed on the n-type Group III nitride crystal layers.

Methods for wet-etching semiconductor samples and devices fabricated from the same are disclosed. The methods can be for selectively wet-etching a semiconductor sample comprising selecting a liquid-phase solution such that when the semiconductor sample is etched with the liquid-phase solution, at least a portion of one of a first doped region or a second doped region is etched at a greater rate than at least a portion of the other of the first doped region or the second doped region; and wet-etching, with the liquid-phase solution, the at least a portion of one of the first doped region or the second doped region at a first etch rate and the at least a portion of the other of the first doped region or the second doped region at a second etch rate; wherein the first etch rate can be greater than the second etch rate.

An etching device may include a reservoir storing an etchant, a support member configured to support the semiconductor wafer in a state where a first surface of the semiconductor wafer is immersed in the etchant, a light source configured to irradiate the first surface of the semiconductor wafer supported by the support member with light emitted from the light source, an electrode disposed in the reservoir, and a power source configured to apply a current between the electrode and the semiconductor wafer supported by the support member, the current changing between a first current value and a second current value larger than the first current value.