A method for processing a semiconductor structure includes: a substrate is provided, which has feature parts, in which an aspect ratio of the feature parts is greater than a preset aspect ratio, a barrier layer is disposed on tops of the feature parts, a hydrophilic layer is disposed on side walls of the feature parts, and there are particulate impurities on a surface of the hydrophilic layer; at least one cleaning treatment to the substrate is performed, in which the cleaning treatment includes: initial water vapor is introduced to the side walls of the feature parts, and a cooling treatment is performed to liquefy the initial water vapor adhering to a surface of the hydrophilic layer into water which carries the particulate impurities and flows into grooves; and a heating treatment is performed to evaporate the water into water vapor which carries the particulate impurities and escapes.

A radiation sensitive composition including a siloxane polymer exhibiting phenoplast crosslinking reactivity as a base resin, which is excellent in resolution and can be used as a radiation sensitive composition capable of allowing a pattern having a desired-shape to be formed with sufficient precision. A radiation sensitive composition including as a silane, a hydrolyzable silane, a hydrolysis product thereof, or a hydrolysis-condensation product thereof; and a photoacid generator, in which the hydrolyzable silane includes hydrolyzable silanes of Formula (1)
R.sup.1.sub.aR.sup.2.sub.bSi(R.sup.3).sub.4-(a+b)  Formula (1)
wherein R.sup.1 is an organic group of Formula (1-2) ##STR00001##
and is bonded to a silicon atom through a Si—C bond or a Si—O bond, and R.sup.3 is a hydrolyzable group; and Formula (2)
R.sup.7.sub.cR.sup.8.sub.dSi(R.sup.9).sub.4-(c+d)  Formula (2)
wherein R.sup.7 is an organic group of Formula (2-1) ##STR00002##
and is bonded to a silicon atom through a Si—C bond or a Si—O bond, and R.sup.9 is a hydrolyzable group.

The present disclosure relates to a patterning method and a method of manufacturing a semiconductor structure. The patterning method includes: providing a base; forming a first patterned mask layer on a surface of the base, where the first patterned mask layer includes a plurality of first mask structures extending along a first direction, and the first mask structures are arranged at intervals; forming a first dielectric layer on the first patterned mask layer, where the first dielectric layer fills up a spacing region between the first mask structures and covers an upper surface of the first patterned mask layer; and etching the first dielectric layer to form a plurality of second mask structures extending along a second direction, where the second mask structures are arranged at intervals, and the second direction intersects with the first direction; and selectively etching the first mask structure and the second mask structure.

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

A method for forming a nanostructure includes coating an exposed surface of a base layer with a patterning layer. The method further includes forming a pattern in the patterning layer including nano-patterned non-random openings, such that a bottom portion of the non-random openings provides direct access to the exposed surface of the base layer. The method also includes depositing a material in the non-random openings in the patterning layer, such that the material contacts the exposed surface to produce repeating individually articulated nano-scale features. The method includes removing remaining portions of the patterning layer. The method further includes forming an encapsulation layer on exposed surfaces of the repeating individually articulated nanoscale features and the exposed surface of the base layer.

A novel dielectric cap structure for VTFET device fabrication is provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a substrate using fin hardmasks, including a first fin(s) and a second fin(s); depositing a liner over the fins and the fin hardmasks; selectively forming first hardmask caps on top of the fin hardmasks/liner over the first fin(s); forming first bottom source and drain at a base of the first fin(s) while the fin hardmasks/liner over the first fin(s) are preserved by the first hardmask caps; selectively forming second hardmask caps on top of the fin hardmasks/liner over the second fin(s); and forming second bottom source and drains at a base of the second fin(s) while the fin hardmasks/liner over the second fin(s) are preserved by the second hardmask caps. A device structure is also provided.

The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.

A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, where a plurality of first trench initial structures are formed on the substrate, and the first trench initial structures extend along a first direction; and sequentially performing a thermal oxidation process and an oxide etching process on trench walls of the first trench initial structures to form first trenches whose trench widths satisfy a first preset dimension. The semiconductor structure and the method for fabricating the same can precisely control a trench width dimension of a trench, to form an isolation structure having a precise dimension in the trench, thereby effectively reducing parasitic capacitance and improving production yield and electrical properties of the semiconductor structure.

A method for forming a semiconductor device is provided. The method includes applying a photoresist composition over a substrate, thereby forming a photoresist layer over the substrate; performing a first baking process to the photoresist layer; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; performing a second baking process to the photoresist layer; and developing the photoresist layer having the pattern therein using a developer, thereby forming a patterned photoresist layer. The first baking process and the second baking process are conducted under an ambient atmosphere having a humidity level ranging from 55% to 100%.