H01L21/31053

Interconnects with tight pitch and reduced resistance

Integrated chips and methods of forming conductive lines thereon include forming parallel lines from alternating first and second dummy materials. Portions of the parallel lines are etched, using respective selective etches for the first and second dummy materials, to form gaps. The gaps are filled with a dielectric material. The first and second dummy materials are etched away to form trenches. The trenches are filled with conductive material.

Surface treatment composition, method for producing surface treatment composition, surface treatment method, and method for producing semiconductor substrate

To provide a means capable of sufficiently removing organic residues present on the surface of a polishing object after polishing containing silicon oxide or polysilicon. A surface treatment composition contains a polymer having a constituent unit represented by Formula (1) below and water and is used for treating the surface of a polishing object after polishing, ##STR00001## in which, in Formula (1) above, R.sup.1 is a hydrocarbon group having 1 to 5 carbon atoms and R.sup.2 is a hydrogen atom or a hydrocarbon group having 1 to 3 carbon atoms.

CHEMICAL-MECHANICAL POLISHING LIQUID
20230104112 · 2023-04-06 ·

Disclosed is a chemical mechanical polishing solution, which contains water, cerium oxide, polyquatemium, carboxylic acid containing a benzene ring and polyvinylamine. The function of auto stop in its true sense can only be achieved by using polyquatemium, carboxylic acid containing a benzene ring and polyvinylamine together. On the blanks, the polishing rates are low, while at the high step heights of patterned silicon chips, high polishing rates are kept. The lower is the step height, the better is the polishing rate inhibited, and thus the function of auto stop is achieved.

Polishing liquid, polishing liquid set and polishing method
11649377 · 2023-05-16 · ·

Provided is a CMP polishing liquid used for removing a part of an insulating portion of a base substrate, which includes a substrate, a stopper provided on one surface of the substrate, and the insulating portion provided on a surface of the stopper opposite to the substrate, by CMP to expose the stopper, the polishing liquid containing: abrasive grains containing cerium; a nonionic water-soluble compound A; a polymer compound B having at least one selected from the group consisting of carboxylic acid groups and carboxylate groups; a basic pH adjusting agent which is optionally contained; and water, in which a content of the basic pH adjusting agent is less than 1.3×10.sup.−2 mol/kg based on the total mass of the polishing liquid.

Structure and method for interconnection with self-alignment

The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

POLISHING LIQUID AND POLISHING METHOD
20230145080 · 2023-05-11 ·

A polishing liquid containing: abrasive grains containing a hydroxide of a tetravalent metal element; a monovalent acid component having no carboxy group; and a non-ionic polymer, in which a pH is 4.5 or less. A polishing method including a step of polishing a surface to be polished by using this polishing liquid.

Polishing composition, production method therefor, and polishing method and production method for substrate, using polishing composition

The present invention provides a polishing composition with which it is possible to decrease a level difference to be unintentionally generated between dissimilar materials and a level difference to be unintentionally generated between coarse and dense portions of a pattern. The present invention relates to a polishing composition which contains abrasive grains having an average primary particle size of 5 to 50 nm, a level difference modifier containing a compound with a specific structure, having an aromatic ring and a sulfo group or a salt group thereof which is directly bonded to this aromatic ring, and a dispersing medium and of which the pH is less than 7.

Method for FinFET fabrication and structure thereof

A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.

ASYMMETRIC FET
20170373148 · 2017-12-28 ·

After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.

COMPOSITION FOR CHEMICAL MECHANICAL POLISHING AND METHOD FOR POLISHING
20230203344 · 2023-06-29 · ·

A composition for chemical mechanical polishing and a polishing method allow a semiconductor substrate containing at least one of a polysilicon film and a silicon nitride film to be polished at a high speed, while being capable of reducing the incidence of surface defects in the polished surface. The composition for chemical mechanical polishing contains (A) abrasive grains having plural protrusions on their surfaces and (B) a liquid medium, wherein the absolute value of the zeta-potential of the component (A) in the composition for chemical mechanical polishing is 10 mV or more.