A polishing liquid containing: abrasive grains; at least one hydroxy acid component selected from the group consisting of a hydroxy acid and a salt thereof; and a compound Z, in which the compound Z has a hydrocarbon group which may be substituted and a polyoxyalkylene group, and a Z value represented by General Formula (1) below is 20 or more:

[00001]$\text{Z = 0}\text{.1}\times {\text{a}}^2\times \text{b/c}.Math.$

[in Formula (1), ″a″ represents the number of carbon atoms of the hydrocarbon group, ″b″ represents the total number of oxyalkylene groups in the compound Z, and ″c″ represents an HLB value of the compound Z.]

The present disclosure relates to a semiconductor packaging method. The method includes: providing a first wafer; and performing a wafer stacking operation a plurality of times. The wafer stacking operation includes: forming a first to-be-bonded wafer in the shape of a boss, where the first to-be-bonded wafer includes a base and a protrusion from the base, and orientating the protrusion toward a second to-be-bonded wafer and bonding the protrusion to the second to-be-bonded wafer; forming a first dielectric layer on a surface of the protrusion; and performing second trimming on an edge region of the protrusion and an edge region of the second to-be-bonded wafer, so that the remainder of the second to-be-bonded wafer after the second trimming is in the shape of a boss, and using the remainder of the wafer stack after the second trimming as the first to-be-bonded wafer for next wafer stacking.

The present invention provides chemical mechanical polishing compositions and methods for polishing a substrate comprising silicon dioxide and silicon nitride, which provide selective removal of SiN relative to silicon oxide (e.g., PETEOS) on patterned wafers. In one embodiment, a CMP method comprises abrading a surface of a substrate comprising SiN and silicon oxide with a CMP composition to remove at least some SiN therefrom. The CMP composition comprises, consists essentially of, or consists of a particulate abrasive (e.g., ceria) suspended in an aqueous carrier and containing a cationic polymer bearing pendant quaternized nitrogen-heteroaromatic moieties, wherein the composition has a pH of greater than about 3.

The present disclosure relates an integrated circuit (IC) and a method for manufacturing same. A polysilicon layer is formed over a first region of a substrate and has a plurality of polysilicon structures that are packed with respect to one another to define a first packing density. A dummy layer is formed over a second region of the substrate and has a plurality of dummy structures that are packed with respect to one another to define a second packing density, where the first packing density and second packing density are substantially similar. An inter-layer dielectric layer is formed over the first region and second region of the substrate. Dishing of at least the second region of the substrate concurrent with a chemical-mechanical polish is generally inhibited by the first packing density and second packing density after forming the inter-layer dielectric layer.

A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate that extends from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; forming a mask layer over the substrate that exposes a portion of the ILD layer and a portion of the outer gate spacer; selectively etching the exposed portion of the outer gate spacer, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process on the exposed portion of the ILD layer to seal the air gap.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. A first gate structure and a second gate structure are across the first and second fins, respectively. An insulating structure is formed between the first gate structure and the second gate structure and includes a first insulating layer separating the first fin from the second fin, a capping structure formed in the first insulating layer, and a second insulating layer covered by the first insulating layer and the capping structure.

The present disclosure provides a slurry. The slurry includes an abrasive including a ceria compound; a removal rate regulator to adjust removal rates of the slurry to metal and to dielectric material; and a buffering agent to adjust a pH value of the slurry, wherein the slurry comprises a dielectric material removal rate higher than a metal oxide removal rate.

A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.

To provide modified colloidal silica capable of improving the stability of the polishing speed with time when used as abrasive grains in a polishing composition for polishing a polishing object that contains a material to which charged modified colloidal silica easily adheres, such as a SiN wafer, and to provide a method for producing the modified colloidal silica.

Modified colloidal silica, being obtained by modifying raw colloidal silica, wherein

the raw colloidal silica has a number distribution ratio of 10% or less of microparticles having a particle size of 40% or less relative to a volume average particle size based on Heywood diameter (equivalent circle diameter) as determined by image analysis using a scanning electron microscope.