A terminal structure of an insulated gate bipolar transistor (IGBT) device includes a main junction, a cutoff ring, and a plurality of terminal rings disposed between the main junction and the cutoff ring, and a resistive element having a first terminal electrically connected to the main junction, a second terminal electrically connected to the cutoff ring, and a plurality of intermediate terminals electrically connected to the terminal rings, respectively. The resistive element is configured to uniformly distribute the lateral voltage between the main junction and the cutoff ring to the terminal rings to ensure that the peak electric field is uniformly distributed across the terminal structure, thereby reducing the terminal structure area and package cost of the IGBT device, while improving the device reliability.

A vertical isolated gate FET transistor integrated in the front end of line of a semiconductor chip is disclosed. In one aspect, the transistor includes a modified version of a buried power rail and back side TSV (through semiconductor via) connection for connecting the front end of line to a back side signal delivery network, such as a power delivery network (PDN), the PDN being arranged on the backside of the semiconductor substrate that carries the active devices of the FEOL on its front side. In contrast to standard power rail/TSV combinations, the TSV is not electrically connected to the rail, but isolated therefrom by a dielectric plug at the bottom of the rail. The TSV is isolated from the semiconductor substrate by a dielectric liner. Well regions are furthermore provided on the front side, enveloping the rail and the dielectric plug, and on the backside, surrounding the TSV and liner. On the back side, the well includes a contact area adjacent the TSV. The TSV thereby acts as the gate of the transistor, while the rail and the contact area respectively act as source and drain or vice versa.

A semiconductor device and a method of making the same is provided. The device includes a semiconductor substrate having a major surface and a back surface. The device also includes a bipolar transistor. The bipolar transistor has a collector region located in the semiconductor substrate; a base region located within the collector region and positioned adjacent the major surface; an emitter region located within the base region and positioned adjacent the major surface; and a collector terminal located on the major surface of the semiconductor substrate. The collector terminal includes: a first electrically conductive part electrically connected to the collector region; an electrically resistive part electrically connected to the first electrically conductive part, and a second electrically conductive part for allowing an external electrical connection to be made the collector terminal. The second conductive part is electrically connected to the first conductive part via the resistive part.

A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

A semiconductor device, including a semiconductor substrate, an active region formed on the semiconductor substrate, and a gate runner disposed to surround the active region. The active region includes a first cell group in which a gate electrode of each cell is directly connected to the gate runner, and a second cell group in which a gate electrode of each cell is connected to the gate runner via a di/dt mitigating element. The di/dt mitigating element is a capacitor, a resistor connected in parallel to a capacitor, or an inverse-parallel-connected diode.

In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Multiple bipolar transistors are disposed side by side in the first direction on a substrate. Multiple first capacitance devices are provided corresponding to the respective base electrodes of the bipolar transistors. A radio frequency signal is supplied to the bipolar transistors through the first capacitance devices. Resistive devices are provided corresponding to the respective base electrodes of the bipolar transistors. A base bias is supplied to the bipolar transistors through the resistive devices. The first capacitance devices are disposed on the same side relative to the second direction orthogonal to the first direction, when viewed from the bipolar transistors. At least one of the first capacitance devices is disposed so as to overlap another first capacitance device partially when viewed in the second direction from the bipolar transistors.

A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

A semiconductor device according to an embodiment includes a semiconductor layer having a first and a second plane; emitter and collector electrode; a trench gate electrode extending in a first direction substantially parallel to the first plane; a dummy trench gate electrode extending in the first direction; a p base region; an emitter region; an n base region; a collector region; a trench gate insulating film; a dummy trench gate electrode; a dummy trench gate insulating film; a first gate pad electrode connected to the trench gate electrode and the dummy trench gate electrode; a first electric resistor connected between the first gate pad electrode and the trench gate electrode, and a second electric resistor connected between the first gate pad electrode and the dummy trench gate electrode. A CR time constant of the trench gate electrode is less than a CR time constant of the dummy trench gate electrode.

Metal pillars are placed adjacent to transistor arrays in the power amplifiers that can be used in wireless devices. By placing the metal pillars in intimate contact with the silicon substrate and not over a substantial portion of the transistor arrays, the heat generated by the transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar forms a solder bump of a flip chip power amplifier die, which when soldered to a module, further conducts the heat away from the transistor array.