A semiconductor device includes a semiconductor substrate having a drift layer of a first conductivity type and a collector layer of a second conductivity type. A first buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the drift layer and the collector layer and a second buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the first buffer layer and the collector layer. A kurtosis of a peak of an impurity concentration of the second buffer layer is lower than a kurtosis of a peak of an impurity concentration of the first buffer layer.

Provided is a testing apparatus for testing a semiconductor device including a first main terminal to which a first power source voltage is applied and a second main terminal to which a second power source voltage is applied, comprising: a condition setting unit for setting a changing speed of a terminal voltage of the first main terminal at turn-off of the device; an operation controlling unit for turning off the device under a condition set by the condition setting unit; and a determining unit for screening the device based on an operation result of the device, wherein: a time waveform of the terminal voltage at turn-off of the device includes a maximum changing point where a changing speed becomes maximum; and the condition setting unit sets the changing speed at a first set voltage higher than a voltage at the maximum changing point, to a predetermined value.

A bipolar semiconductor device includes at least a four-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact separated from the first main side by at least a base layer of first conductivity type. A shorting layer of the first conductivity type is arranged on the second main side of the base layer. A third layer includes a patterned highly conductive material, such as metal and/or silicides, graphene, etc., and is deposited on the shorting. A fourth layer of the second conductivity type is arranged directly on the third layer, inserted between the shorting layer and the second electrical contact. This concept can be applied to any non-punch-through or punch-through reverse conducting IGBT designs, but is particularly effective for devices using thin wafers, and is also applicable to bipolar diodes in order to improve a soft recovery process.

A semiconductor device including a transistor section and a diode section, the semiconductor device having: a temperature sensing section; a neighboring transistor section adjacent to the temperature sensing section; a neighboring diode section adjacent to the temperature sensing section; and a first non-neighboring diode section that is not adjacent to the temperature sensing section, wherein the first non-neighboring diode section has a pattern different from the pattern of the neighboring diode section in the top view is provided.

A semiconductor device has transistor portions and diode portions. The transistor portions have a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type, second semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, a first semiconductor layer of the first conductivity type, a third semiconductor region of the second conductivity type, a first electrode, and a second electrode. The diode portions have the semiconductor substrate, the first semiconductor region, the first semiconductor layer, a fourth semiconductor region of the first conductivity type, the first electrode, and the second electrode. The first semiconductor layer has a predetermined region, a depth of the predetermined region from a second main surface of the semiconductor substrate is greater than a depth of a region of the first semiconductor layer excluding the predetermined region, from the second main surface of the semiconductor substrate.

Provided is a semiconductor device including a semiconductor substrate; a gate trench portion formed in a front surface of the semiconductor substrate; a dummy trench portion formed in the front surface of the semiconductor substrate; and a first front-surface-side electrode that includes metal and is formed above the front surface of the semiconductor substrate. The gate trench portion includes a gate trench formed in the front surface of the semiconductor substrate; a gate conducting portion formed inside the gate trench; and a gate insulating portion that is formed above the gate conducting portion inside the gate trench and provides insulation between the gate conducting portion and the first front-surface-side electrode. The dummy trench portion includes a dummy trench formed in the front surface of the semiconductor substrate; and a dummy conducting portion that is formed inside the dummy trench and contacts the first front-surface-side electrode.

A semiconductor device includes a semiconductor body, a first electrode, a control electrode and a control interconnection electrically connected to the control electrode. The first electrode, the control electrode, and the control interconnection are provided on a front surface side of the semiconductor body. The control electrode is shaped as one body in a trench. The control electrode includes a first portion, a second portion, a first end portion and a second end portion that are arranged in a direction along the front surface of the semiconductor body. The first and second portions are positioned between the first and second end portions. The first portion is positioned between the first electrode and the semiconductor body, and the second portion is positioned between the control interconnection and the semiconductor body. The control interconnection crosses the second portion of the control electrode, and is electrically connected thereto.

Provided is a semiconductor device, wherein: in a semiconductor substrate, a lifetime control region is provided from at least a part of a transistor portion to a diode portion; the transistor portion includes a main region, a boundary region located between the main region and the diode portion and overlapped with the lifetime control region, and a plurality of gate trench portions; the plurality of gate trench portions include a first gate trench portion provided in the main region and a second gate trench portion provided in the boundary region; and a gate resistance component of the first gate trench portion is different from a gate resistance component of the second gate trench portion.

A vertical electrostatic discharge protection device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, a first doped buried layer, a second semiconductor epitaxial layer, a first doped well, at least one second doped well, and a first heavily-doped area. The epitaxial layers are stacked on the substrate. The first doped buried layer is formed in the first semiconductor epitaxial layer. The first doped well is formed in the second semiconductor epitaxial layer. The first doped well is formed on the first doped buried layer, and the doping concentration of the first doped well is lower than that of the first doped buried layer. The second doped well is formed in the second semiconductor epitaxial layer. The second doped well is adjacent to the first doped well.

A vehicle powertrain includes an IGBT that conducts current between a supply and load. The vehicle powertrain also includes a controller that applies voltage to a gate of the IGBT at a first level for a first duration that depends on a capacitance of the gate, and increases the voltage over a second duration based on a rate of change of the current falling below a threshold defined by a supply voltage for the load.