In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.

In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.

A semiconductor device including: drift regions formed on a semiconductor substrate; gate trench portions extending in predetermined extending directions from a semiconductor substrate upper surface; first and second mesa portions being in direct contact with one and the other sides of a gate trench portion side wall respectively; accumulation regions being in direct contact with the gate trench portions, above the drift regions, and having doping concentration higher than drift region concentration; a base region being in direct contact with the gate trench portions, above the accumulation regions; emitter regions being in direct contact with the one side wall of a gate trench portion on a semiconductor substrate upper surface in the first mesa portion, and having doping concentration higher than drift region concentration; and electrically floating second conductivity type floating regions provided spaced from the gate trench portion below the base region in the second mesa portion is provided.

In a semiconductor device, a boundary area is between an IGBT region and a diode region. In other words, the boundary region is at a position adjacent to the diode region. The boundary region has a lower ratio of formation of a high-concentration P-type layer than the IGBT region. Accordingly, during recovery, hole injection from the IGBT region to the diode region can be inhibited. The reduced ratio of formation of the high-concentration P-type layer in the boundary region also reduces the amount of hole injection from the high-concentration P-type layer of the boundary region. Thus, it inhibits an increase in maximum reverse current during the recovery, and also decreases the carrier density on the cathode side to inhibit an increase in tail electrical current, so that the semiconductor device reduces switching loss and is highly resistant to recovery destruction.

A transient voltage protection circuit includes a first input/output pad, a second input/output pad, and a trigger circuit coupled between the first input/output pad and the second input/output pad. The trigger circuit includes a first trigger element which includes a first input/output node, a second input/output node, a third input/output node, and a first substrate diode coupled to the third input/output node of the first trigger element. The trigger circuit further includes a first resistor coupled between the first input/output node of the first trigger element and the second input/output node of the first trigger element. The trigger circuit further includes a second trigger element which includes a first input/output node, a second input/output node, a third input/output node, wherein the second input/output node of the first trigger element is coupled to the first input/output node of the second trigger element, and a second substrate diode coupled to the third input/output node of the second trigger element. The trigger circuit further includes a second resistor coupled between the first input/output node of the second trigger element and the second input/output node of the second trigger element.

A semiconductor device includes: an insulating substrate including an insulating layer of which a first metal layer and a second metal layer are provided on both surfaces; a semiconductor element provided on the first metal layer; and an external connection terminal bonded to the first metal layer, the external connection terminal being electrically insulated from the second metal layer, wherein: the first metal layer includes a main portion being in contact with the insulating layer, the semiconductor element being provided in the main portion, and a protruding portion protruding from the main portion, the external connection terminal being bonded to the protruding portion; and at least a part of the protruding portion is provided to protrude from an outer peripheral edge of the insulating layer in a plan view of the insulating substrate.

A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.

A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.

A semiconductor device including: drift regions formed on a semiconductor substrate; gate trench portions extending in predetermined extending directions from a semiconductor substrate upper surface; first and second mesa portions being in direct contact with one and the other sides of a gate trench portion side wall respectively; accumulation regions being in direct contact with the gate trench portions, above the drift regions, and having doping concentration higher than drift region concentration; a base region being in direct contact with the gate trench portions, above the accumulation regions; emitter regions being in direct contact with the one side wall of a gate trench portion on a semiconductor substrate upper surface in the first mesa portion, and having doping concentration higher than drift region concentration; and electrically floating second conductivity type floating regions provided spaced from the gate trench portion below the base region in the second mesa portion is provided.

A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer on the drift layer; a collector layer and a cathode layer arranged on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and reaching the drift layer, and arranged along one direction; a gate electrode arranged in each trench via a gate insulating film; and an emitter region arranged in a surface portion of the base layer, and contacting with each trench. The semiconductor substrate includes an IGBT region having the emitter region and an FWD region in which an injection limiting region and a contact region are arranged in the surface portion of the base layer alternately along the one direction.