An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

A silicon carbide semiconductor device has a termination region, which includes first to fourth semiconductor regions, one provided on the outer side of another. The second semiconductor region has first small regions that are provided in a region having an impurity concentration lower than that of the first semiconductor region, and have the same impurity concentration as first semiconductor region. The third semiconductor region has a lower impurity concentration than the first semiconductor region. The fourth semiconductor region has second small regions that have the same impurity concentration as the third semiconductor region. A width of the first semiconductor region is narrower than a width of the third semiconductor region.

The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

There is disclosed a structure in a wide band gap material such as silicon carbide wherein there is a buried grid and shields covering at least one middle point between two adjacent parts of the buried grid, when viewed from above. Advantages of the invention include easy manufacture without extra lithographic steps compared with standard manufacturing process, an improved trade-off between the current conduction and voltage blocking characteristics of a JBSD comprising the structure.

The present disclosure is directed to a diode with a semiconductor body of silicon including a cathode region, which has a first conductivity type and is delimited by a front surface; and an anode region, which has a second conductivity type and extends into the cathode region from the front surface. The diode further includes a barrier region of cobalt disilicide, arranged on the anode region; and a metallization region of aluminum or of an aluminum alloy, arranged on the barrier region. The barrier region contacts the anode region.

There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.

A semiconductor device according to the present disclosure includes: a gate electrode provided in a gate trench and provided so as to oppose a source region via a gate insulating film; a first bottom protection region of a second conductivity type provided below the gate insulating film; a plurality of first connection regions of the second conductivity type provided at a first interval in an extension direction of the gate trench and electrically connecting the first bottom protection region and a body region; a Schottky electrode provided in a Schottky trench; a second bottom protection region of the second conductivity type provided below the Schottky electrode; and a plurality of second connection regions of the second conductivity type provided at a second interval smaller than the first interval in an extension direction of the Schottky trench and electrically connecting the second bottom protection region and the body region.

The disclosure provides a superjunction IGBT (insulated gate bipolar transistor) device, wherein a carrier storage layer of a first conductivity type is provided between a voltage sustaining layer and a base region, and a MISFET (metal-insulator-semiconductor field effect transistor) of a second conductivity type is also integrated in a cell, with at least one gate of the MISFET is connected to the emitter contact thereof. The MISFET is turned off at a low forward conduction voltage, helping to reduce the conduction voltage drop. The MISFET can provide a path for carriers of a second conductivity type and prevent the carrier storage layer from suffering a high electric field when the forward conduction voltage is slightly higher or it is at the forward blocking state, helping to improve the reliability.

Disclosed is a manufacturing method of a trench-type power device. The manufacturing method comprises: forming a drift region; forming a first trench and a second trench in the drift region; forming a gate stack in the first trench; forming a doped region and a well region of P type in the drift region by performing first ion implantation; forming a source region of N type in the well region by performing second ion implantation. The well region in which a dopant concentration gradually decreases with depth is formed by the first ion implantation, an upper part of the well region is inverted by the second ion implantation to form the source region. The doped region and well region can be formed by self-alignment in a common ion implantation step, improving power device performance, reducing numbers of process steps of ion implantation and masks, reducing manufacturing cost.

Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.