A semiconductor device includes a semiconductor body having a first surface and second surface opposite to the first surface in a vertical direction, and a plurality of transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes at least two source regions, first and second gate electrodes spaced apart from each other in a first horizontal direction and arranged adjacent to and dielectrically insulated from a continuous body region, a drift region separated from the at least two source regions by the body region, and at least three contact plugs extending from the body region towards a source electrode in the vertical direction. The at least three contact plugs are arranged successively between the first and second gate electrodes. Only the two outermost contact plugs that are arranged closest to the first and second gate electrodes, respectively, directly adjoin at least one of the source regions.

A method for forming a superjunction power semiconductor device includes forming multiple epitaxial layers of a first conductivity type on a semiconductor substrate and implanting dopants of a second conductivity type into each epitaxial layer to form a first group of implanted regions in a first region and a second group of implanted regions in a second region in each epitaxial layer. The multiple epitaxial layers are annealed to form multiple columns of the second conductivity type having slanted sidewalls across the first to last epitaxial layers. The columns include a first group of columns formed by the implanted regions of the first group and having a first grading and a second group of columns formed by the implanted regions of the second group and having a second grading, where the second grading is less than the first grading.

A semiconductor device includes a first electrode, a first semiconductor region connected to the first electrode and being of a first conductivity type, a second semiconductor region provided on the first semiconductor region, contacting the first semiconductor region and being of a second conductivity type, first metal layers and second metal layers provided on the second semiconductor region and contacting the second semiconductor region, a third semiconductor region provided between the first semiconductor region and the first metal layer, and a second electrode. The third semiconductor region contacts the first and second semiconductor regions and being of the first conductivity type. An impurity concentration of the third semiconductor region is greater than an impurity concentration of the first semiconductor region. The second electrode contacts the first semiconductor region, the second semiconductor region, the first metal layers, and the second metal layers.

A super-junction device and a method of fabricating such a device are disclosed, in which a pillar of a second conductivity type situated at an interface between a transition region and a core region is narrowed in width across at least an upper thickness thereof, thereby reducing peak electric field strength in the transition region, increasing voltage endurance of the transition region and preventing the occurrence of avalanche breakdown first in the transition region. Additionally, a dopant ion concentration profile increasing in the direction from the transition region to the core region is created across upper portions of some pillars of the second conductivity type in the core region, which increases the presence of the dopant of the second conductivity type around the surface of the core region and thus stops a vertical electric field before it can reach wells of the second conductivity type. That is, an effective epitaxial thickness of the core region is reduced, which results in lower voltage endurance thereof. In this way, it is ensured that avalanche breakdown occurs first in the core region, resulting in improved EAS performance.

A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

An improved SiC trench MOSFET having first and second type gate trenches for formation of a gate electrode, and a grounded P-shield region under the gate electrode for gate oxide electric-field reduction is disclosed. The gate electrodes are disposed into the first type gate trench having a thick oxide layer on trench bottom. The grounded P-shield region surrounding the second type gate trench filled up with the thick oxide layer is connected with a source metal through a grounded P region. The device further comprises a current spreading region surrounding the first type gate trench for on-resistance reduction.

Disclosed is a superjunction semiconductor device and a method for manufacturing the same and, more particularly, to a superjunction semiconductor device and a method for manufacturing the same seeking to improve on-resistance characteristics of the device without degrading breakdown voltage characteristics by forming a second conductivity type impurity region on and/or in a surface of a substrate in a cell region C to increase a second conductivity type impurity concentration in the device.

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs formed in an epitaxial layer. Each MOSFET includes source and body regions and a contact trench formed between first and second gate trenches. A region of the epitaxial layer between the gate trenches extends to the top surface of the epitaxial layer. An insulated gate electrode is formed in each gate trench. At least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region.

A silicon carbide semiconductor device includes a silicon carbide substrate having a first principal surface and a second principal surface opposite to the first principal surface. The silicon carbide substrate includes a drift region, a body region, and a source region. A gate trench is provided on the first principal surface, the gate trench being defined by: a side surface, which passes through the source region and the body region and reaches the drift region; and a bottom surface coupled to the side surface. The silicon carbide substrate further includes a first reduced-electric field region provided between the bottom surface and the second principal surface and having a second conductive type. The source region includes a first region contacting the side surface, the first region having a first thickness. The source region includes a second region having a second thickness greater than the first thickness, the first region being interposed between the side surface and the second region. The silicon carbide semiconductor device further includes a contact electrode with an ohmic junction with the second region.

Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.