A silicon carbide semiconductor device, including a semiconductor substrate, and a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions and a plurality of fourth semiconductor regions formed in the semiconductor substrate. The semiconductor device further includes a plurality of trenches penetrating the second, third and fourth semiconductor regions, a plurality of gate electrodes respectively provided via a plurality of gate insulating films in the trenches, a plurality of fifth semiconductor regions each provided between one of the gate insulating films at the inner wall of one of the trenches, and the third semiconductor region and the fourth semiconductor region through which the one trench penetrates. The semiconductor device further includes first electrodes electrically connected to the second, third and fourth semiconductor regions, and a second electrode provided on a second main surface of the semiconductor substrate.

The present disclosure can be applied to semiconductor devices and, in particular, relates to a MOSFET device made of silicon carbide and a method for manufacturing same. A metal-oxide film semiconductor field-effect transistor device of the present disclosure may comprise: a drain electrode; a substrate arranged on the drain electrode; an N-type drift layer arranged on the substrate; a current-spreading layer arranged on the drift layer; P-type well layers arranged on the current-spreading layer to define a channel; an N+ region arranged on the well layers; a damage prevention layer adjacent to the N+ region and having a lower N-type doping concentration than that of the N+ region; a P+ region arranged on one side of the channel; a gate oxide layer arranged on the current-spreading layer; a gate layer arranged on the gate oxide layer; and a source electrode arranged on the gate layer.

In semiconductor device, a field plate portion having a high concentration p-type semiconductor region, a low concentration p-type semiconductor region having a lower impurity concentration than the high concentration p-type semiconductor region and a high concentration n-type semiconductor region is provided. Then, the high concentration p-type semiconductor region is electrically connected to the source region while the high concentration n-type semiconductor region is electrically connected to the drain region.

To provide a technique capable of improving performance and reliability of a semiconductor device. An n.sup.−-type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p.sup.+-type body region (14), n.sup.+-type current spreading regions (16, 17), and a trench. TR are formed in the n.sup.−-type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p.sup.+-type body region (14), a side surface S1 of the trench TR is in contact with the n.sup.+-type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n.sup.+-type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the n.sup.−-type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface 32 of the trench. Furthermore, an angle θ1 at which the upper surface T1 of the n.sup.−-type epitaxial layer (12) is inclined with respect to the side surface S1 is smaller than an angle θ2 at which the upper surface T1 of the n.sup.−-type epitaxial layer (12) is inclined with respect to the side surface S2.

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs formed in an epitaxial layer. Each MOSFET includes source and body regions and a contact trench formed between first and second gate trenches. A region of the epitaxial layer between the gate trenches extends to the top surface of the epitaxial layer. An insulated gate electrode is formed in each gate trench. At least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region.

A method for manufacturing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes etching a gate stack comprising a first nitride layer. The first nitride layer is on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack is oxidized to form a polysilicon layer from the silicon layer, and to form a second oxide layer on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer is formed conformingly covering the second oxide layer. A nitride etch-stop layer is formed conformingly covering the second nitride layer.

Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm≤Lxr≤0.20 μm holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.

Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.

A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode.

A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.