The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).

Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

A silicon carbide semiconductor device includes a silicon carbide substrate and a gate electrode. The silicon carbide substrate includes a first source region and a second source region, a first body region, a second body region, a first drift region, a second drift region, a third drift region, and a first connection region. The first connection region is provided to include a first intersection and a second intersection, the first intersection being an intersection of a straight line along a first straight-line portion and a straight line along a second straight-line portion, the second intersection being an intersection of a straight line along a third straight-line portion and a straight line along a fourth straight-line portion, and the first connection region has a second conductivity type.

A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path.

A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.

A semiconductor device includes a power transistor in a semiconductor substrate portion, where the semiconductor substrate portion includes a central portion and a kerf, components of the power transistor are arranged in the central portion, and the central portion has a thickness d. The semiconductor device also includes a support element disposed over a main surface of the central portion, where the support element has a smallest lateral extension t at a side adjacent to the main surface of the semiconductor substrate portion and a height h, where 0.1×h≦d≦4×h and 0.1×h≦t≦1.5×h.

A MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the semiconductor substrate and the epitaxial layer. In a p-type body layer provided in a surface portion of the epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer. An n-type drift layer is provided in a surface portion of the epitaxial layer in spaced relation from the body layer. An n-type drain layer is provided in a surface portion of the epitaxial layer in contact with the n-type drift layer. A p-type buried layer having a lower impurity concentration than the n-type buried layer is buried in the epitaxial layer between the drift layer and the n-type buried layer in contact with an upper surface of the n-type buried layer.

A semiconductor device includes: a substrate; a drift region disposed on a principal surface of the substrate; a first well region extending from a second principal surface of the drift region in a direction perpendicular to the second principal surface and having a bottom portion; a second well region being in contact with the bottom portion and disposed at a portion inside the substrate located below the bottom portion; and a source region extending in a perpendicular direction from a region of the second principal surface provided with the first well region, and reaching the second well region. In a direction parallel to the second principal surface and oriented from a source electrode to a drain electrode, a distance of the second well region in contact with a gate insulating film is shorter than a distance of the first well region in contact with the gate insulating film.

A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.