The present disclosure describes a semiconductor device with counter-doped nanostructures and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, the fin structure including one or more first-type nanostructures and one or more second-type nanostructures. The method further includes forming a polysilicon structure over the fin structure and forming a source/drain (S/D) region on a portion of the fin structure and adjacent the polysilicon structure, the S/D region including a first dopant. The method further includes doping the one or more second-type nanostructures with a second dopant via a space released by the polysilicon structure and the one or more first-type nanostructures, where the second dopant is opposite to the first dopant. The method further includes replacing portions of the one or more doped second-type nanostructures with additional second-type nanostructures.

A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.

A semiconductor device and a method of fabricating the same are proposed. The semiconductor device includes a plurality of hole-channel Group III nitride devices and a plurality of electron-channel Group III nitride devices. In the above, the hole-channel Group III nitride devices and the electron-channel Group III nitride devices are arranged in correspondence with each other. The electron-channel Group III nitride device has a fin-shaped channel, and a two-dimensional hole gas and/or a two-dimensional electron gas can be simultaneously formed at an interface between a compound semiconductor layer and a nitride semiconductor layer.

Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.

The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern.

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.

A semiconductor device includes: a substrate; a source region and a drain region located in the substrate; a gate structure located in the substrate between the source region and the drain region; an insulating layer located between the gate structure and the drain region; a plurality of field plates located on the insulating layer, wherein the field plate closest to the gate structure is electrically connected to the source region; a first well region located in the substrate; a body contact region located in the first well region, wherein the body contact region is electrically connected to the source region and the field plate closest to the gate structure; and a first doped drift region located in the substrate, wherein the gate structure is located between the first well region and the first doped drift region, and the drain region is located in the first doped drift region.

A semiconductor device includes: a semiconductor layer having a main surface; a first-conduction-type well region formed on a surface portion of the main surface of the semiconductor layer; a second-conduction-type first region formed on a surface portion of the well region; a second-conduction-type second region formed on the surface portion of the well region at an interval from the first region; a first-conduction-type diffusion layer formed on the surface portion of the main surface adjacent to the first region; a planar gate structure formed on the main surface of the semiconductor layer to face a first-conduction-type channel region between the first region and the second region; and a memory structure including a charge storage film arranged adjacent to a lateral side of the planar gate structure on a side of the first region.