A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body, removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C., and forming a first load terminal structure at the first side of the semiconductor body.

A method of forming a power semiconductor device includes: arranging a control electrode at least partially on or inside a semiconductor body; forming elevated source regions in the semiconductor body by: implanting first conductivity type dopants into the semiconductor body; forming a recess mask layer covering at least areas of intended source regions; and removing portions of the semiconductor body uncovered by the recess mask layer to form the elevated source regions and recessed body regions at least partially between the source regions. A dielectric layer is formed on the semiconductor body. A contact hole mask layer is formed on the dielectric layer. Portions of the dielectric layer uncovered by the contact hole mask layer are removed to form a contact hole which is filled at least partially with a conductive material to establish an electrical contact with at least a portion of the elevated source and recessed body regions.

An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n.sup.+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.

A method of manufacturing a reverse-blocking IGBT (insulated gate bipolar transistor) includes forming a plurality of IGBT cells in a device region of a semiconductor substrate, forming a reverse-blocking edge termination structure in a periphery region of the semiconductor substrate which surrounds the device region, etching one or more trenches in the periphery region between the reverse-blocking edge termination structure and a kerf region of the semiconductor substrate, depositing a p-type dopant source which at least partly fills the one or more trenches and diffusing p-type dopants from the p-type dopant source into semiconductor material surrounding the one or more trenches, so as to form a continuous p-type doped region in the periphery region which extends from a top surface of the semiconductor substrate to a bottom surface of the semiconductor substrate after thinning of the semiconductor substrate at the bottom surface.

A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10.sup.−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

A method of processing a semiconductor device includes: creating first and second recesses in a surface of a semiconductor body; creating an insulation layer that forms first and second wells each having a common lateral extension range with the portion of the insulation layer located between the recesses; filling the wells with a plug material having the respective common lateral extension range with the insulation layer; removing a middle portion of the insulation layer located between the recesses; filling, with a filling material, a third recess created in a region where the middle portion has been removed and at least a portion of the space located between the wells; creating a first common surface of the insulation layer, the plug material, and the filling material; removing the plug material from the second well; and creating a second insulation layer that covers a side wall of the second recess.

To provide a highly reliable semiconductor device having both an improved breakdown voltage and a reduced withstand voltage leakage current. An intermediate resistive field plate is comprised of a first intermediate resistive field plate coupled, at one end thereof, to an inner-circumferential-side resistive field plate and, at the other end, to an outer-circumferential-side resistive field plate and a plurality of second intermediate resistive field plates. The first intermediate resistive field plate has a planar pattern that is equipped with a plurality of first portions separated from each other in a first direction connecting the inner-circumferential resistive field plate to the outer-circumferential-side resistive field plate and linearly extending in a second direction orthogonal to the first direction, and repeats reciprocation along the second direction. The second intermediate resistive field plates are each connected with a first end portion on one side of the first portions and extend with a curvature.

A semiconductor device includes a vertical gate electrode in a gate trench in a semiconductor substrate, and a lateral gate electrode over the semiconductor substrate and adjacent the gate trench, where the lateral gate electrode results in improved electrical performance of the semiconductor device. The improved electrical performance includes an improved avalanche current tolerance in the semiconductor device. The improved electrical performance includes a reduced impact ionization under the gate trench. The improved electrical performance includes a reduced electric field under the gate trench. The lateral gate electrode results in an improved thermal stability in the semiconductor device.

A semiconductor device according to the present invention includes a channel region of a first conductivity type, disposed at a front surface portion of a semiconductor layer, an emitter region of a second conductivity type, disposed at a front surface portion of the channel region, a drift region of the second conductivity type, disposed in the semiconductor layer at a rear surface side of the channel region, a collector region of the first conductivity type, disposed in the semiconductor layer at a rear surface side of the drift region, a gate trench, formed in the semiconductor layer, a gate electrode, embedded in the gate trench, and a convex region of the second conductivity type, projecting selectively from the drift region to the channel region side at a position separated from a side surface of the gate trench.

There are disclosed herein various implementations of a bipolar semiconductor device with sub-cathode enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type opposite the first conductivity type. The bipolar semiconductor device also includes first and second depletion trenches, each having a depletion electrode. In addition, the bipolar semiconductor device includes a first control trench situated between the first and second depletion trenches, the first control trench extending into the drift region and being adjacent to cathode diffusions. An enhancement region having the first conductivity type is localized in the drift region between the first control trench and one or both of the first and second depletion trenches. In one implementation, the bipolar semiconductor device may be an insulated-gate bipolar transistor (IGBT).