A semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer, a gate electrode, a silicide barrier, a source contact plug, a drain contact plug, and a field plate plug. The gate insulating layer, disposed between the drain region and the source region, includes a first gate insulating layer having a first thickness and a second gate insulating layer having a second thickness larger than the first thickness. A bottom surface of the first gate insulating layer and a bottom surface of the second gate insulating layer are parallel to each other. The gate electrode is disposed on the first and second gate insulating layers. The silicide barrier layer is disposed in contact with a top surface of the second gate insulating layer and a top surface of the gate electrode. The source contact plug is connected to the source region.

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

A semiconductor device includes: a substrate; a source region and a drain region located in the substrate; a gate structure located in the substrate between the source region and the drain region; an insulating layer located between the gate structure and the drain region; a plurality of field plates located on the insulating layer, wherein the field plate closest to the gate structure is electrically connected to the source region; a first well region located in the substrate; a body contact region located in the first well region, wherein the body contact region is electrically connected to the source region and the field plate closest to the gate structure; and a first doped drift region located in the substrate, wherein the gate structure is located between the first well region and the first doped drift region, and the drain region is located in the first doped drift region.

A semiconductor device according to the present disclosure includes a P layer, an insulating film, an electrode, a plurality of P- layers arranged on a side of a termination region of the P layer, an N- layer, an N++ layer, an insulating film, an electrode, a high permittivity layer disposed at least on the P- layers, and a low permittivity layer disposed on the high permittivity layer, and a distance between an end on a side of an active region of the insulating film and an end on a side of the termination region of one of the P- layers located farthest from the active region is more than .Math.m and .Math.m or less, and a distance between the end on the side of the active region of the insulating film and an end on a side of the active region of the electrode is 50 .Math.m or more.

A semiconductor structure includes a semiconductor substrate, a trench being provided in the semiconductor substrate, and a gate being formed in the trench; an ion implantation layer located in the semiconductor substrate outside the trench, a top surface of the ion implantation layer being higher than that of the gate, and a bottom surface of the ion implantation layer being lower than the top surface of the gate and higher than a bottom surface of the gate; a transition layer located between the gate and the ion implantation layer, a bottom surface of the transition layer being lower than the top surface of the gate and higher than the bottom surface of the gate, and a doping concentration of the transition layer being lower than that of the ion implantation layer.

A lateral diffused metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a second fin-shaped structure adjacent to the first fin-shaped structure, a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, a first gate structure on the first fin-shaped structure, a second gate structure on the second fin-shaped structure, and an air gap between the first gate structure and the second gate structure.

A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.

A semiconductor device includes an active gate metal structure disposed over a substrate, the active gate metal structure having a first sidewall and a second sidewall opposite to each other. The semiconductor device includes a first source/drain region disposed adjacent the first sidewall of the active gate metal structure with a first lateral distance. The semiconductor device includes a second source/drain region disposed adjacent the second sidewall of the active gate metal structure with a second lateral distance, wherein the second lateral distance is substantially greater than the first lateral distance. The semiconductor device includes a resist protective oxide (RPO) comprising a first portion extending over a portion of a major surface of the substrate that is laterally located between the second sidewall and the second source/drain region, wherein the RPO has no portion extending over a top surface of the active gate metal structure.

A semiconductor substrate has a surface and a convex portion projecting upward from the surface. An n-type drift region has a portion located in the convex portion. The n.sup.−-type drain region has a higher n-type impurity concentration than the n-type drift region, and is arranged in the convex portion and on the n-type drift region such that the n.sup.−-type drain region and a gate electrode sandwich the n-type drift region in plan view.

Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping.