Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

A thin film transistor 101 includes: a gate electrode 2, a semiconductor layer 4 disposed on the gate electrode via a gate insulating layer 3, a source electrode 8s disposed on a portion of the semiconductor layer 4 via a first contact layer Cs, and a drain electrode 8d disposed on another portion via a second contact layer Cd. The first and second contact layers have a multilayer structure including N (where N is an integer equal to or greater than 1) two-layer structures S(n) (where n is an integer not smaller than 1 and not greater than N), each two-layer structure S(n) including a first amorphous silicon layer 71 that is directly in contact with the source or drain electrode, a second amorphous silicon layer 72(n), and a third amorphous silicon layer 73(n) that is directly in contact with an upper face thereof. In each two-layer structure S(n), n type impurity concentrations C2(n) and C3(n) of the second amorphous silicon layer and the third amorphous silicon layer and an n type impurity concentration C1 of the first amorphous silicon layer satisfy C2(n)<C3(n)<C1 for any given n.

The disclosure provides a thin-film transistor, a manufacturing method thereof, an array substrate and a display panel, and belongs to the technical field of thin-film transistor devices. The thin-film transistor includes a base substrate, an active layer on the base substrate including a plurality of semiconductor nanowires, and a plurality of guiding projections on the base substrate which extend along a first direction and are arranged at intervals and each of which includes two side walls extending along the first direction, and the semiconductor nanowire extends along a side wall of the guiding projection. In the thin-film transistor, since the semiconductor nanowires are used as the active layer, mobility and concentration of carriers in the thin-film transistor can be effectively increased and therefore performance of the thin-film transistor can be improved. A length of the semiconductor nanowire is not limited, and a size of the thin-film transistor is not limited.

A manufacturing apparatus and a manufacturing method are provided. A manufacturing apparatus includes a chamber, and a stage disposed in the chamber. The stage includes an upper surface on which a target substrate is disposed, a lower surface opposite to the upper surface, a first side surface extending between the upper surface and the lower surface in a first direction, and a second side surface extending between the upper surface and the lower surface in a second direction perpendicular to the first direction. The first side surface is in a round shape, and at least a portion of the first side surface is convex toward an outside of the stage.

Disclosed are a thin film transistor, a display apparatus comprising the thin film transistor, and a method for manufacturing the thin film transistor. The thin film transistor comprises an active layer, and a gate electrode spaced apart from the active layer and configured to have at least a portion overlapped with the active layer, wherein the active layer includes a silicon semiconductor layer, and an oxide semiconductor layer which contacts the silicon semiconductor layer, wherein at least a portion of the silicon semiconductor layer and at least a portion of the oxide semiconductor layer are overlapped with the gate electrode.

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

A manufacturing apparatus and a manufacturing method are provided. A manufacturing apparatus includes a chamber, and a stage disposed in the chamber. The stage includes an upper surface on which a target substrate is disposed, a lower surface opposite to the upper surface, a first side surface extending between the upper surface and the lower surface in a first direction, and a second side surface extending between the upper surface and the lower surface in a second direction perpendicular to the first direction. The first side surface is in a round shape, and at least a portion of the first side surface is convex toward an outside of the stage.

An anti-stress liquid crystal display structure and a manufacturing method are provided. The anti-stress liquid crystal display structure includes a first substrate, a plurality of thin film transistors, a second substrate, a plurality of pillar-shaped supporting elements, and a liquid crystal layer. The plurality of thin film transistors have a protection layer and include at least one first protruding part and at least one first concave part. One end of each of the pillar-shaped supporting elements is connected to the second substrate, and other end of each of the pillar-shaped supporting elements includes at least one second protruding part and at least one second concave part and is disposed on the protection layer of each of the thin film transistors. The liquid crystal layer is disposed between the first substrate and the second substrate.

A display device may include a substrate, a buffer layer on the substrate, a first active pattern on the buffer layer, the first active pattern having a first thickness, a second active pattern on the buffer layer spaced from the first active pattern and having a second thickness smaller than the first thickness, a first gate insulating layer on the first active pattern and the second active pattern, a first gate electrode on the first gate insulating layer, the first gate electrode overlapping the first active pattern, and a second gate electrode on the first gate insulating layer, the second gate electrode overlapping the second active pattern.

Provided are a driving backplane, a method for manufacturing the same and a display device. The driving backplane includes a substrate, a first gate disposed on a side of the substrate, an active layer disposed on a side of the first gate away from the substrate, and a second gate disposed on a side of the active layer away from the substrate. An orthographic projection of the second gate on the substrate is located in an orthographic projection of the first gate on the substrate, and in a direction parallel to the substrate, an edge of an orthographic projection of the first gate on the substrate extends beyond an edge of the orthographic projection of the second gate on the substrate.