Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.

Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO.sub.2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO.sub.2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

A method for manufacturing a semiconductor device having a junction field effect transistor, includes: preparing a substrate having a first conductivity type drift layer; forming a first conductivity type channel layer above the drift layer by an epitaxial growth, to thereby produce a semiconductor substrate; forming a second conductivity type gate layer within the channel layer by performing an ion-implantation; forming a second conductivity type body layer at a position separated from the gate layer within the channel layer by performing an ion-implantation; and forming a second conductivity type shield layer at a position that is to be located between the gate layer and the drift layer within the channel layer by performing an ion-implantation. The shield layer is formed to face the gate layer while being separated from the gate layer, and is kept to a potential different from that of the gate layer.

A power transistor device includes a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region and a gate region in the mesa adjacent the channel region. The channel region and the source layer have the first conductivity type, and the gate region has a second conductivity type opposite the first conductivity type. The channel region includes a deep conduction region and a shallow conduction region between the deep conduction region and the gate region. The deep conduction region has a first doping concentration, and the shallow conduction region has a second doping concentration that is greater than the first doping concentration.

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

A vertical FET device includes a semiconductor structure comprising a semiconductor substrate, a first semiconductor layer coupled to the semiconductor substrate, and a second semiconductor layer coupled to the first semiconductor layer. The vertical FET device also includes a plurality of fins. Adjacent fins of the plurality of fins are separated by a trench extending into the second semiconductor layer and each of the plurality of fins includes a channel region disposed in the second semiconductor layer. The vertical FET also includes a gate region extending into a sidewall portion of the channel region of each of the plurality of fins, a source metal structure coupled to the second semiconductor layer, a gate metal structure coupled to the gate region, and a drain contact coupled to the semiconductor substrate.

A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.

A Vertical Function Field Effect Transistor (VIFET) is disclosed with reduced noise and input capacitance and high input impedance. The VIFET has a substrate; a source disposed on the substrate; a drain, and a channel. The vertical channel has one or more channel sidewall surfaces. The channel sidewall surfaces have a total or aggregate channel sidewall surface area. A semiconductor gate grown on one or more of the channel sidewall surfaces has a thickness below 10 nanometers (nm), or between 3 am and 10 om, that reduces transistor noise. The interface surface area between the conductive (e.g. metal) external electrical gate contact and the contacted surface of the semiconductor gate is minimized to further reduce transistor noise.