A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.

A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.

Vertical MOSFET and JFET devices are incorporated on the same chip, enabling circuit designs that benefit from the simultaneous use of such devices. A fabrication method allows formation of the devices using a shared source/drain layer on a bulk semiconductor substrate.

A semiconductor device includes: an n type layer disposed on a first surface of a substrate; an n+ type region disposed on the n type layer; a trench disposed on the n type layer; a p type region disposed adjacent to a side surface of the trench and extending to a part under a lower surface of the trench; an auxiliary n+ type region disposed under the lower surface of the trench and disposed in the p type region; an auxiliary electrode disposed at the lower surface of the trench; a gate electrode separated from the auxiliary electrode and disposed on the lower surface of the trench; a source electrode disposed on the n+ type region; and a drain electrode disposed at a second surface of the substrate.

Vertical MOSFET and JFET devices are incorporated on the same chip, enabling circuit designs that benefit from the simultaneous use of such devices. A fabrication method allows formation of the devices using a shared source/drain layer on a bulk semiconductor substrate.

A JFET transistor device having a reduced pitch may be manufactured using self-alignment techniques, while avoiding misalignments that may lead to decreased breakdown voltage and/or increased R.sub.DSon. Consequently, described devices provide, for a given active area and gate voltage, additional current channels, increased current, and reduced R.sub.DSon, as compared to conventional devices, while retaining high BV.sub.gs values.

Vertical MOSFET and JFET devices are incorporated on the same chip, enabling circuit designs that benefit from the simultaneous use of such devices. A fabrication method allows formation of the devices using a shared source/drain layer on a bulk semiconductor substrate.