Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.

Semiconductor structure and a method for fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate, a doped source layer formed in the substrate; a channel pillar formed on the doped source layer; a gate structure formed on the sidewall surface of the channel pillar; a first contact layer, having a first thickness and formed at the surface of the doped source layer; and a second contact layer having a second thickness and formed on the top surface of the channel pillar. The first thickness is greater than the second thickness.

A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.

An RC IGBT includes, in an active region, an IGBT section and at least three diode sections. The arrangement of the diode sections obeys a design rule.

We herein describe a semiconductor device comprising a first element portion formed on a substrate, the first element portion being an operating region of an insulated gate bipolar transistor (IGBT) and a second element portion formed on the substrate, the second element portion being an operating region of a diode. The first element portion comprises a first collector region of a second conductivity type, a drift region of a first conductivity type located over the first collector region, and formed by the semiconductor substrate, a first body region of a first conductivity type located over the drift region, a second body region of a second conductivity type located over the drift region, at least one first contact region of a first conductivity type located above the second body region and having a higher doping concentration compared to the first body region, at least one second contact region of a second conductivity type located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the second body region, a first plurality of trenches extending from a surface through the second body region of a second conductivity type into the drift region wherein the at least one first contact region adjoins at least one of the plurality of trenches so that, in use, a channel region is formed along said at least one trench of the first plurality of trenches and within the body region of a second conductivity type. A first trench of the first plurality of trenches is laterally spaced from a second trench of the first plurality of trenches by a first distance. The second element portion comprises a second collector region of a second conductivity type, the drift region of a first conductivity type located over the second collector region, a third body region of a second conductivity type located over the drift region, a second plurality of trenches extending from a surface through the third body region into the drift region. A first trench of the second plurality of trenches is laterally spaced from a second trench of the second plurality of trenches by a second distance, and the first distance is larger than the second distance. The semiconductor device further comprises a first terminal contact, wherein the first terminal contact is electrically connected to the at least one first contact region of a first conductivity type and the body region of a second conductivity type and a second terminal contact, wherein the second terminal contact is electrically connected to the first collector region and the second collector region.

A semiconductor component includes: a SiC semiconductor body; a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body, the trench having a conductive connection structure, a structure width at a bottom of the trench, and a dielectric layer covering sidewalls of the trench; a shielding region along the bottom and having a central section which has a lateral first width; and a contact formed between the conductive connection structure and the shielding region. The conductive connection structure is electrically connected to a source electrode. In at least one doping plane extending approximately parallel to the bottom, a dopant concentration in the central section deviates by not more than 10% from a maximum value of the dopant concentration in the shielding region in the doping plane. The first width is less than the structure width and is at least 30% of the structure width.

A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

An insulated gate bipolar transistor includes a P-type group III-V nitride compound layer. An N-type group III-V nitride compound layer contacts a side of the P-type group III-V nitride compound layer. An HEMT is disposed on the N-type group III-V nitride compound layer. The HEMT includes a first group III-V nitride compound layer disposed on the N-type group III-V nitride compound layer. A second group III-V nitride compound layer is disposed on the first group III-V nitride compound layer. A source is embedded within the second group III-V nitride compound layer and the first group III-V nitride compound layer, wherein the source includes an N-type group III-V nitride compound body and a metal contact. A drain contacts another side of the P-type group III-V nitride compound layer. A gate is disposed on the second group III-V nitride compound layer.

A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.