To provide a highly reliable semiconductor device having both an improved breakdown voltage and a reduced withstand voltage leakage current. An intermediate resistive field plate is comprised of a first intermediate resistive field plate coupled, at one end thereof, to an inner-circumferential-side resistive field plate and, at the other end, to an outer-circumferential-side resistive field plate and a plurality of second intermediate resistive field plates. The first intermediate resistive field plate has a planar pattern that is equipped with a plurality of first portions separated from each other in a first direction connecting the inner-circumferential resistive field plate to the outer-circumferential-side resistive field plate and linearly extending in a second direction orthogonal to the first direction, and repeats reciprocation along the second direction. The second intermediate resistive field plates are each connected with a first end portion on one side of the first portions and extend with a curvature.

A silicon carbide epitaxial layer includes: a first impurity region; a second impurity region; and a third impurity region. A gate insulating film is in contact with the first impurity region, the second impurity region, and the third impurity region. A groove portion is formed in a surface of the first impurity region, the surface being in contact with the gate insulating film, the groove portion extending in one direction along the surface, a width of the groove portion in the one direction being twice or more as large as a width of the groove portion in a direction perpendicular to the one direction, a maximum depth of the groove portion from the surface being not more than 10 nm.

A semiconductor device according to the present invention includes a channel region of a first conductivity type, disposed at a front surface portion of a semiconductor layer, an emitter region of a second conductivity type, disposed at a front surface portion of the channel region, a drift region of the second conductivity type, disposed in the semiconductor layer at a rear surface side of the channel region, a collector region of the first conductivity type, disposed in the semiconductor layer at a rear surface side of the drift region, a gate trench, formed in the semiconductor layer, a gate electrode, embedded in the gate trench, and a convex region of the second conductivity type, projecting selectively from the drift region to the channel region side at a position separated from a side surface of the gate trench.

To improve the performance of a semiconductor device having an IGBT. A p.sup.+-type collector layer is formed on the back surface side of a semiconductor substrate. A back electrode is formed over the back surface of the semiconductor substrate. Within the semiconductor substrate, an n.sup.−-type drift region is formed over the p.sup.+-type collector layer, and a first IGBT cell region and a second IGBT cell region are formed on the surface side of the semiconductor substrate. An embedded insulating film is formed on the surface side of the semiconductor substrate between the first IGBT cell region and the second IGBT cell region. An interlayer insulating film is formed over the first IGBT cell region, the second IGBT cell region, and the embedded insulating film. An emitter electrode is formed over the interlayer insulating film.

In an embodiment, a process of forming an electronic device can include providing a semiconductor substrate having a first major side and an electronic component at least partly within the semiconductor substrate along the first major side; The process can further include thinning the semiconductor substrate to define a second major surface along a second major side opposite the first major side; and selectively removing a portion of the semiconductor substrate along the second major side to define a trench having a distal surface. The process can further include forming a feature adjacent to or within the trench. The feature can include a doped region, a conductive structure, or the like. In another embodiment, an electronic device can include the semiconductor substrate and a conductive structure within a trench. The conductive layer can laterally surround a pillar within the trench.

A semiconductor device includes first and second load contacts and a semiconductor region extending along an extension direction. A surface region is arranged above and coupled to the semiconductor region. At least one control electrode is arranged within the surface region. At least one connector trench extends into the semiconductor region along the extension direction and includes a connector electrode. A contact pad is arranged within the surface region. A contact runner is arranged within the surface region and placed separately from both the contact pad and the at least one control electrode, the contact pad, the contact runner and the at least one control electrode being electrically coupled to each other. Either both the contact pad and the contact runner or both the contact runner and the at least one control electrode are electrically connected to the connector electrode of the at least one connector trench.

A semiconductor device includes: a trench; a first electrode is formed in the trench; a first impurity region, which has a first conductivity type and is formed to abut on the trench; a second impurity region, which has a second conductivity type and is formed to abut the trench; an insulating film, which is formed on the front surface of the semiconductor substrate; a conductive plug, which is formed to penetrate through the insulating film and is electrically connected to the first impurity region and the second impurity region; wherein the conductive plug includes: a silicon layer made of silicon other than a single crystal; a silicide crystallite contained in the silicon layer; and a blocking layer that is formed to cover sides of the silicon layer and is made of a material that is impervious to the silicide crystallites.

Inside an IGBT using GaN or SiC, light having an energy of approximately 3 [eV] is generated. Therefore, defects are caused in the gate insulating film of the IGBT. Furthermore, the charge trapped at a deep level becomes excited and moves to the channel region, thereby causing the gate threshold voltage to fluctuate from the predetermined value. Provided is a semiconductor device including a normally-ON semiconductor element that includes a first semiconductor layer capable of conductivity modulation and a first gate electrode, but does not include a gate insulating film between the first gate electrode and the first semiconductor layer; and a normally-OFF semiconductor element that includes a second semiconductor layer, a second gate electrode, and a gate insulating film between the second semiconductor layer and the second gate electrode. The normally-ON semiconductor element and the normally-OFF semiconductor element are connected in series.

A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor device further includes a transistor structure in the semiconductor body and a source contact structure overlapping the transistor structure. The source contact structure is electrically connected to source regions of the transistor structure. A gate contact structure is further provided, which has a part separated from the source contact structure by a longitudinal gap within a lateral plane. Gate interconnecting structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and a gate electrode of the transistor structure. Electrostatic discharge protection structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and the source contact structure. At least one of the gate interconnecting structures is between two of the electrostatic discharge protection structures along a length direction of the longitudinal gap.

A semiconductor device includes first and second electrodes and a silicon carbide layer located between the first and second electrodes. A plurality of gate electrodes is interposed between the first electrode and the silicon carbide layer and extends in a first direction. The silicon carbide layer includes a plurality of spaced apart openings having sidewalls and a base which extend inwardly between the gate electrodes, a first region containing a second conductivity type impurity extending around and under the openings, and a second region containing a second conductivity type impurity interposed between the portion of the first region extending under the base of the openings. The concentration of the second conductivity type impurity is greater in the second region than in the first region. The silicon carbide layer includes a third region containing a first conductivity type impurity extending inwardly of the first region from the sidewall of the openings.