Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.

In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n.sup.− drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.

One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.

A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Log.sub.e (L.sup.2/SD), the dispersion degree is not less than 2 and not more than 15.

Provided is a semiconductor device that includes a drift region that is of a first conductivity type and is provided in a semiconductor substrate; a base region that is of a second conductivity type and is provided above the drift region; an accumulation region that is of the first conductivity type provided between the base region and the drift region; and an electric field relaxation region that is provided between the base region and the accumulation region, wherein the boundary between the electric field relaxation region and the accumulation region is a location for a half-value for the peak of the doping concentration of the accumulation region, and an integrated concentration of the electric field relaxation region is greater than or equal to 5E14 cm.sup.−2 and less than or equal to 5E15 cm.sup.−2.

Provided is a semiconductor device, including: a semiconductor substrate including a bulk donor; an active portion provided on the semiconductor substrate; and an edge termination structure portion provided between the active portion and an end side of the semiconductor substrate on a upper surface of the semiconductor substrate; wherein the active portion includes hydrogen, and has a first high concentration region with a higher donor concentration than a bulk donor concentration; and the edge termination structure portion, which is provided in a range that is wider than the first high concentration region in a depth direction of the semiconductor substrate, includes hydrogen, and has a second high concentration region with a higher donor concentration than the bulk donor concentration.

A semiconductor device including: a semiconductor substrate; a temperature sensing unit provided on a front surface of the semiconductor substrate; an anode pad and a cathode pad electrically connected with the temperature sensing unit; a front surface electrode being set to a predetermined reference potential; and a bidirectional diode unit electrically connected in a serial bidirectional way between the cathode pad and the front surface electrode is provided. The output comparison diode unit may be arranged between the anode pad and the cathode pad. The temperature sensing unit may include a temperature sensing diode, and the output comparison diode unit may include a diode connected in inverse parallel to the temperature sensing diode.

The present disclosure relates to an insulated gate bipolar transistor (IGBT) and, more particularly, to an insulated gate bipolar transistor, in which a barrier region is in a mesa between adjacent trench gates to divide the width of the mesa, thereby inducing the accumulation of hole carriers, and thus reducing an on-resistance (e.g., of the IGBT).