A vertical MOSFET having a trench gate structure includes an n.sup.-type drift layer and a p-type base layer formed by epitaxial growth. In the n.sup.-type drift layer, an n-type region, a first p.sup.+-type region, and a second p.sup.+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p.sup.+-type region is provided between the source electrode and the p-type base layer.

A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.

A semiconductor device includes an electrically conductive lead frame which includes a die pad and a plurality of electrically conductive leads, each of the leads in the plurality being spaced apart from the die pad. The semiconductor device further includes first and second integrated switching devices mounted on the die pad, each of the first and second integrated switching devices include electrically conductive gate, source and drain terminals. The source terminal of the first integrated switching device is disposed on a rear surface of the first integrated switching device that faces and electrically connects with the die pad. The drain terminal of the second integrated switching device is disposed on a rear surface of the second integrated switching device that faces and electrically connects with the die pad.

A semiconductor device includes a semiconductor body having first and second opposite sides, a drift region, a body layer at the second side, and a field-stop region in Ohmic connection with the body layer. A source metallization at the second side is in Ohmic connection with the body layer. A drain metallization at the first side is in Ohmic connection with the drift region. A gate electrode at the second side is electrically insulated from the semiconductor body to define an operable switchable channel region in the body layer. A through contact structure extends at least between the first and second sides, and includes a conductive region in Ohmic connection with the gate electrode and a dielectric layer. In a normal projection onto a horizontal plane substantially parallel to the first side, the field-stop region surrounds at least one of the drift region and the gate electrode.

A vertical conduction junction transistor apparatus includes a multilayered semiconductor unit cell that has a substrate, epitaxial drift layer, epitaxial channel layer, gate region and channel control region. The substrate is silicon carbide (SiC). The epitaxial drift layer comprises SiC and is formed on the top surface of the substrate. The epitaxial channel layer comprises SiC and is formed on a top surface of the epitaxial drift layer, where a sidewall of the epitaxial channel layer is at an angle to the vertical direction. The gate region is formed in the sidewall of the epitaxial channel layer, the gate region having an inner gate region boundary that is parallel to the sidewall. The channel control region is in the epitaxial channel layer and has a width bounded by the inner gate region boundary. The channel control region has a trapezoidal cross-section in a plane taken in the vertical direction.

In an embodiment, a semiconductor device is provided that includes a semiconductor body having a first conductivity type, a first major surface and a second major surface opposite the first major surface, a gate arranged on the first major surface, a body region having a second conductivity type opposite the first conductivity type, the body region extending into the semiconductor body from the first major surface, a source region having the first conductivity type, the source region being arranged in the body region, a buried channel shielding region having the second conductivity type, a contact region having the second conductivity type, and a field plate arranged in a trench extending into the semiconductor body from the first major surface.

A method for manufacturing a semiconductor device includes the steps of forming a metal film (Ni film) over the bottom surface of a contact hole that exposes a portion including SiC at the bottom surface, and performing a heat treatment to form a silicide film at the bottom surface of the contact hole by a silicidation reaction of the metal film MT and the portion including SiC. Also, the heat treatment step is a step of irradiating a laser beam on the surface of a SiC substrate. As the heat treatment, annealing is performed using the laser beam that goes through SiC and is absorbed by metal (Ni and the like).

An embodiment relates to a device comprising a first section and a second section. The first section comprises a first metal oxide semiconductor (MOS) interface comprising a first portion and a second portion. The first portion comprises a first contact with a horizontal surface of a semiconductor substrate and the second portion comprises a second contact with a trench sidewall of a trench region of the semiconductor substrate. The second section comprises one of a second metal oxide semiconductor (MOS) interface and a metal region. The second MOS interface comprises a third contact with the trench sidewall of the trench region. The metal region comprises a fourth contact with a first conductivity type drift layer. The first section and the second section are located contiguously within the device along a lateral direction.

A semiconductor device includes an electrically conductive lead frame which includes a die pad and a plurality of electrically conductive leads, each of the leads in the plurality being spaced apart from the die pad. The semiconductor device further includes first and second integrated switching devices mounted on the die pad, each of the first and second integrated switching devices include electrically conductive gate, source and drain terminals. The source terminal of the first integrated switching device is disposed on a rear surface of the first integrated switching device that faces and electrically connects with the die pad. The drain terminal of the second integrated switching device is disposed on a rear surface of the second integrated switching device that faces and electrically connects with the die pad.

A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.