Semiconductor devices, and in particular protection structures for semiconductor devices that include sensor arrangements are disclosed. A semiconductor device may include a sensor region, for example a current sensor region that occupies a portion of an overall active area of the device. The current sensor region may be configured to provide monitoring of device load currents during operation. Semiconductor devices according to the present disclosure include one or more protection structures that are configured to allow the semiconductor devices to withstand transient voltage events without device failure. A protection structure may include an insulating layer that is provided in a transition region between a device region and the sensor region of the semiconductor device. In the example of an insulated gate semiconductor device, the insulating layer of the protection structure may include a material with a greater breakdown voltage than a breakdown voltage of a gate insulating layer.

A semiconductor device includes first and second insulated-gate transistors in parallel with each other, a charger-discharger, and a gate voltage correction circuit. The charger-discharger can perform first control to charge both of the gates of the first and second transistors, second control to discharge both of the gates of the first and second transistors, and third control to charge one of the gates of the first and second transistors. The gate voltage correction circuit corrects the gate voltages of the first and second transistors to eliminate the difference between those voltages in at least one of the first control, the second control, and protection operation in which the first and second transistors are forcibly kept off.

The sense region is spaced from the active region. The isolation trench surrounds the sense region and isolates the sense region from the active region. The active region is provided with a first gate trench defined by a first side surface and a first bottom surface continuing to the first side surface. The first insulating film is in contact with both the first side surface and the first bottom surface. The first conductor is provided on the first insulating film. The second insulating film is provided in the isolation trench. The second conductor is provided on the second insulating film. The isolation trench reaches a first impurity region. The first insulating film is made of a material identical to that of the second insulating film. The first conductor is made of a material identical to that of the second conductor and is electrically isolated from the second conductor.

A power semiconductor device includes a semiconductor layer, a ladder-shaped trench recessed a specific depth from a surface of the semiconductor layer into the semiconductor layer and including a pair of lines having a first depth and a plurality of connectors connected between the pair of lines and having a second depth shallower than the first depth, a well region defined in the semiconductor layer between the pair of lines and between the plurality of connectors of the trench, a floating region defined in the semiconductor layer outside the pair of lines of the trench, a gate insulating layer disposed on an inner wall of the trench, and a gate electrode layer disposed on the gate insulating layer to fill the trench and including a first portion in which the pair of lines is filled and a second portion in which the plurality of connectors is filled. A depth of the second portion of the gate electrode layer is shallower than a depth of the first portion of the gate electrode layer.

A main semiconductor device element is a vertical MOSFET with a trench gate structure, containing silicon carbide as a semiconductor material, and having first and second p.sup.+-type regions that mitigate electric field applied to bottoms of trenches. The first p.sup.+-type regions are provided separate from the p-type base regions and face the bottoms of the trenches in a depth direction. The first p.sup.+-type regions are disposed at an interval that is at most 1.0 μm, in a first direction that is a direction in which gate electrodes extend. The second p.sup.+-type regions are provided between adjacent trenches of the trenches, separate from the first p.sup.+-type regions and the trenches, and in contact with the p-type base regions. In the first direction that is the direction in which the trenches, the second p.sup.+-type regions extend in a linear shape having a length that is substantially equal to that of the trenches.

A semiconductor device having, in a main non-operating region that is free of unit cells of a main semiconductor element, a gate insulating film and a gate electrode of a current sensing portion extending on a front surface of a semiconductor substrate, to thereby form a planar gate structure. A gate capacitance of the planar gate structure is a gate capacitance of the current sensing portion. Directly beneath the planar gate structure, at the front surface of the semiconductor substrate, a structure is provided in which, from a front side of the semiconductor substrate, a p-type region, an n-type region, and a p-type region are stacked, whereby electric field is not applied to the extended portions of the gate insulating film.

Semiconductor device includes an element region in which the semiconductor element is provided, a semiconductor substrate including an outer peripheral region surrounding the element region, a plurality of semiconductor elements provided in an array-like in the element region. The element region includes a main circuit region in which the main circuit of semiconductor device is formed, and a sense circuit region in which a sense circuit for measuring the drain current flowing through the semiconductor element of the main circuit region is formed. Semiconductor element of the sense circuit region is surrounded by other semiconductor elements. Sense circuit region is covered with a main circuit source electrode which is connected to the semiconductor element of the main circuit region.

A semiconductor device includes a semiconductor layer of first-conductivity-type that has a main surface and that includes an active region set at the main surface, a current detection region set at the main surface away from the active region, and a boundary region set in a region between the active region and the current detection region at the main surface, a first body region of second-conductivity-type formed in a surface layer portion of the main surface at the active region, a first trench gate structure formed in the main surface at the active region, a second body region of second-conductivity-type formed in the surface layer portion of the main surface at the current detection region, a second trench gate structure formed in the main surface at the current detection region, a well region of second-conductivity-type formed in the surface layer portion of the main surface at the boundary region, and a dummy trench gate structure formed in an electrically floating state in the main surface at the boundary region.

A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.

There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.