A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a first conductive type buried layer disposed on a substrate; a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer; a source region disposed in the second conductive type body region; a drain region disposed in the first conductive type deep well region; and a gate electrode disposed on the second conductive type body region and the first conductive type drift region.

A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

A vertical insulated-gate field effect transistor includes a semiconductor substrate and a gate electrode on a first surface thereof. This gate electrode has a plurality of eight (or more) sided openings extending therethrough. Each of these openings has eight (or more) sidewalls, including a first plurality of sidewalls that are flat relative to a center of the opening and second plurality of sidewalls that are either flat or concave relative to the center of the opening. A source electrode is also provided, which extends into the openings. This source electrode may ohmically contact a source region within the semiconductor substrate. If the field effect transistor is a JBSFET, the source electrode may also form a Schottky rectifying junction with a drift region within the semiconductor substrate.

A wide gap semiconductor device has: a first MOSFET region (M0) having a first gate electrode 10 and a first source region 30 provided in a first well region 20 made of a second conductivity type; a second MOSFET region (M1) provided below a gate pad 100 and having a second gate electrode 110 and a second source region 130 provided in a second well region 120 made of the second conductivity type; and a built-in diode region electrically connected to the second gate electrode 110. The second source region 130 of the second MOSFET region (M1) is electrically connected to the gate pad 100.

Semiconductor devices, and more particularly semiconductor devices with improved edge termination structures are disclosed. A semiconductor device includes a drift region that forms part of an active region. An edge termination region is arranged along a perimeter of the active region and also includes a portion of the drift region. The edge termination region includes one or more sub-regions of an opposite doping type than the drift region and one or more electrodes may be capacitively coupled to the drift region by way of the one or more sub-regions. During a forward blocking mode for the semiconductor device, the one or more electrodes may provide a path that draws ions away from passivation layers that are on the edge termination region and away from the active region. In this manner, the semiconductor device may exhibit reduced leakage, particularly at higher operating voltages and higher associated operating temperatures.

A SiC integrated circuit structure which allows multiple power MOSFETs or LDMOSs to exist in the same piece of semiconductor substrate and still function as individual devices which form the components of a given circuit architecture, for example, and not by limitation, in a half-bridge module. In one example, a deep isolation trench is etched into the silicon carbide substrate surrounding each individual LDMOS device. The trench is filled with an insulating material. The depth of the trench may be deeper than the thickness of an epitaxial layer to ensure electrical isolation between the individual epitaxial layer regions housing the individual LDMOSs. The width of the trench may be selected to withstand the potential difference between the bias levels of the body regions of neighboring power LDMOS devices.

According to an embodiment of a semiconductor device, the device includes: a transistor or diode device formed in a semiconductor substrate; an insulating material at least partially covering a lateral drift zone of the transistor or diode device or a termination region; and a fill pattern disposed over the lateral drift zone or termination region, the fill pattern having a variable density that follows equipotential lines of an electric field distribution expected between the fill pattern at a surface of the lateral drift zone or termination region during operation of the semiconductor device. Corresponding methods of producing the semiconductor device are also described.

An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

LDMOS device including a drift region, a body region, a gate dielectric layer, a polysilicon gate, a source region, a drain region and a common dielectric layer, the common dielectric layer covers a portion, between a second side of the polysilicon gate and the drain region, of the surface of the drift region, extends onto the surface of the polysilicon gate and also covers part of the surface of the drain region, a self-aligned metal silicide is formed on portions, not covered by the common dielectric layer, of the surfaces of the polysilicon gate, the source region and the drain region, and the common dielectric layer serves as a growth barrier layer of the self-aligned metal silicide; a drain terminal field plate is formed on a portion of the surface of the common dielectric layer; and a portion of the common dielectric layer serves as a field plate dielectric layer.

A semiconductor device is provided. The semiconductor device includes a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.