It is provided a driving system, a driving method, a computer system and a computer readable medium. The driving system includes: an input circuit configured to receive an input on-chip voltage and output the on-chip voltage; an adjusting circuit configured to automatically detect a present amplitude of the on-chip voltage output by the input circuit and to output a bias voltage corresponding to the present amplitude of the on-chip voltage to a gate of the driven thin film transistor, wherein a source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage. The protection of the transistor gate and the adjusting of a receiver threshold voltage for different I/O (input/output) voltages and levels can be completed through automatic detection of the on-chip voltage and automatic adjusting.

A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

An illustrative bidirectional MOSFET switch includes a body region, a buried layer, a gate terminal, and a configuration switch. The body region is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type. The buried layer is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type. The gate terminal is drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal. The configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

Considering ease of electrical conduction tests and the like, electrodes provided mainly above an active region are desirably continuous on a single plane. A semiconductor device is provided, including: a semiconductor substrate; a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein the second top surface electrode has: a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and a second connecting portion that connects the first region and the second region above the first connecting portion.

IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.

A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.

The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD protection for high voltage IC. Wherein said the device comprises a P substrate, a P well, a N well, a first field oxide isolation region, a first P+ injection region, a second field oxide isolation region, a first N+ injection region, a first fin polysilicon gate, a second N+ injection region, a second fin polysilicon gate, a third N+ injection region, a third fin polysilicon gate, a polysilicon gate, a fourth fin polysilicon gate, a second P+ injection region, a fifth fin polysilicon gate, a third P+ injection region, a sixth fin polysilicon gate, a fourth P+ injection region, a third oxygen isolation region, a fourth N+ injection region and a fourth field oxygen isolation region. Under the influence of ESD pulse, the ESD discharge current path with LDMOS-SCR structure and the RC coupling current path with embedded PMOS interdigital structure in the drain terminal and embedded NMOS interdigital structure in the source terminal are formed, in order to enhance the ESD robustness of the device and improve the voltage clamp capability.