An illustrative bidirectional MOSFET switch includes a body region, a buried layer, a gate terminal, and a configuration switch. The body region is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type. The buried layer is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type. The gate terminal is drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal. The configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

To provide a high-withstand-voltage lateral semiconductor device in which ON-resistance or drain current density is uniform at an end portion and a center portion of the device in a gate width direction. A lateral N-type MOS transistor 11 formed on an SOI substrate includes a trench isolation structure 10b filled with an insulating film at an end portion of the transistor. An anode region 6 of a diode 12 is provided adjacent to a P-type body region 1 of the transistor through the trench isolation structure 10b and a cathode region 15 of the diode 12 is also provided adjacent to an N-type drain-drift region 4 of the transistor through the trench isolation structure 10b so as to cause electric field to be applied to the trench isolation structure 10b to be zero when a voltage is applied across the transistor.

An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.

The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD protection for high voltage IC. Wherein said the device comprises a P substrate, a P well, a N well, a first field oxide isolation region, a first P+ injection region, a second field oxide isolation region, a first N+ injection region, a first fin polysilicon gate, a second N+ injection region, a second fin polysilicon gate, a third N+ injection region, a third fin polysilicon gate, a polysilicon gate, a fourth fin polysilicon gate, a second P+ injection region, a fifth fin polysilicon gate, a third P+ injection region, a sixth fin polysilicon gate, a fourth P+ injection region, a third oxygen isolation region, a fourth N+ injection region and a fourth field oxygen isolation region. Under the influence of ESD pulse, the ESD discharge current path with LDMOS-SCR structure and the RC coupling current path with embedded PMOS interdigital structure in the drain terminal and embedded NMOS interdigital structure in the source terminal are formed,in order to enhance the ESD robustness of the device and improve the voltage clamp capability.

IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.

Considering ease of electrical conduction tests and the like, electrodes provided mainly above an active region are desirably continuous on a single plane. A semiconductor device is provided, including: a semiconductor substrate; a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein the second top surface electrode has: a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and a second connecting portion that connects the first region and the second region above the first connecting portion.

A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.

An illustrative bidirectional MOSFET switch includes a body region, a buried layer, a gate terminal, a first configuration switch, and a second configuration switch. The body region is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type. The buried layer is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type. The gate terminal is drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal. The first configuration switch disconnects the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage; and the second configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

A power stage, comprising of multiple power MOSFETs and control and monitoring circuits, is an important part of voltage regulators. The voltage regulator controller typically monitors the power stage output current to implement control and protection functions. Traditional power stages mostly adapt monolithic solutions, suffering from performance inefficiencies due to the LDMOS process, while co-packaged solutions with combined VDMOS and LDMOS processes suffer from potential large current monitoring errors due to different operating temperatures. The current invention proposes a current monitoring circuit with temperature compensation to cancel the temperature coefficient mismatch between the external power MOSFET and the current monitoring circuit. Therefore, the gain of the current monitoring circuit doesn't change with the temperature, allowing for high current monitoring precision, and the temperature compensation circuit doesn't affect the bandwidth of the current monitoring circuit, allowing the use of the output current monitoring signal for close-loop control and over-current protection.