An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

A semiconductor device with favorable electrical characteristics, a semiconductor device with stable electrical characteristics, or a highly reliable semiconductor device or display device is provided. A first insulating layer and a first conductive layer are stacked over a first region of a first metal oxide layer. A first layer is formed in contact with a second metal oxide layer and a second region of the first metal oxide layer that is not overlapped by the first insulating layer. Heat treatment is performed to lower the resistance of the second region and the second metal oxide layer. A second insulating layer is formed. A second conductive layer electrically connected to the second region is formed over the second insulating layer. Here, the first layer is formed to contain at least one of aluminum, titanium, tantalum, and tungsten.

A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

A semiconductor device with high on-state current and high reliability is provided. The semiconductor device includes first to fifth insulators, first to third oxides, and first to fourth conductors; the fifth insulator includes an opening in which the second oxide is exposed; the third oxide is placed in contact with a bottom portion of the opening and a side portion of the opening; the second insulator is placed in contact with the third oxide; the third conductor is provided in contact with the second insulator; the third insulator is placed in contact with a top surface of the third conductor and the second insulator; and the fourth conductor is in contact with the third insulator and the top surface of the third conductor and placed in the opening.

A display device and a method of manufacturing a display device are provided. A display device includes a lower conductive pattern disposed on a substrate, a lower insulating layer disposed on the lower conductive pattern, the lower insulating layer including a first lower insulating pattern including an overlapping region overlapping the lower conductive pattern, and a protruding region. The display device includes a semiconductor pattern disposed on the first lower insulating pattern and having a side surface, the side surface being aligned with a side surface of the first lower insulating pattern or disposed inward from the side surface of the first lower insulating pattern, a gate insulating layer disposed on the semiconductor pattern, a gate electrode disposed on the gate insulating layer, and an empty space disposed between the substrate and the protruding region of the first lower insulating pattern.

A pixel includes a light emitting element, a driving switching element and a first compensation switching element and a second compensation switching element. The driving switching element is which applies a driving current to the light emitting element. The first compensation switching element and the second compensation switching element are connected between a control electrode of the driving switching element and an output electrode of the driving switching element. The first compensation switching element and the second compensation switching element are connected to each other in series. The driving switching element is a P-type transistor. The first compensation switching element is an N-type transistor. The second compensation switching element is a P-type transistor.

A method of fabricating a device includes providing a fin having a stack of epitaxial layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. A source/drain etch process is performed to remove portions of the stack of epitaxial layers in source/drain regions to form trenches that expose lateral surfaces of the stack of epitaxial layers. A dummy layer recess process is performed to laterally etch the plurality of dummy layers to form recesses along sidewalls of the trenches. An inner spacer material is deposited along sidewalls of the trenches and within the recesses. An inner spacer etch-back process is performed to remove the inner spacer material from the sidewalls of the trenches and to remove a portion of the inner spacer material from within the recesses to form inner spacers having a dish-like region along lateral surfaces of the inner spacers.

According to one embodiment, a semiconductor device includes a gate electrode, a first insulating layer covering the gate electrode, an oxide semiconductor provided on the first insulating layer immediately above the gate electrode, a source electrode in contact with the oxide semiconductor, and a drain electrode in contact with the oxide semiconductor. Each of the source electrode and the drain electrode includes an oxide conductive layer in contact with the oxide semiconductor, a first metal layer stacked on the oxide conductive layer, a second metal layer formed of a different material from the first metal layer and stacked on the first metal layer, and a third metal layer formed of a same material as the first metal layer and stacked on the second metal layer.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A display device and method of fabricating the same are provided. The display device includes a substrate and a thin-film transistor formed on the substrate. The thin-film transistor includes a lower gate conductive layer disposed on the substrate, and a lower gate insulating film disposed on the lower gate conductive layer The lower gate insulating film includes an upper surface and sidewalls. The thin-film transistor includes an active layer disposed on the upper surface of the lower gate insulating film, the active layer including sidewalls. At least one of the sidewalls of the lower gate insulating film and at least one of the sidewalls of the active layer are aligned with each other.