A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

A field-effect transistor (FET) and a radio-frequency module are provided comprising an active region comprising a source region, a drain region, a body region disposed between the source region and the drain region, a first body extension portion in contact with the body region, a second body extension portion in contact with the body region, and a body contact region in contact with the first extension portion and the second extension portion; and a gate disposed on a top surface of the body region. A die is also provided comprising two or more such FETs.

A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

An array substrate, its manufacturing method, and a display apparatus are provided. The array substrate having a substrate, includes: a monocrystalline silicon substrate employed as the substrate including a central display area, a first peripheral area, and a second peripheral area; substrate circuits integrated with a scan drive circuit in the first peripheral area, a data drive circuit in the second peripheral area, and a plurality of pixel circuits in the central display area; a plurality of scan lines in the central display area and coupled to the scan drive circuit; and a plurality of data lines in the central display area and coupled to the data drive circuit. The scan drive circuit, the data drive circuit, and the plurality of pixel circuits include a plurality of transistors, each of which has an active region inside the monocrystalline silicon layer.

A transistor comprises a pair of source/drain regions having a channel region there-between. A transistor gate construction is operatively proximate the channel region. The channel region comprises a direction of current flow there-through between the pair of source/drain regions. The channel region comprises at least one of GaP, GaN, and GaAs extending all along the current-flow direction. Each of the source/drain regions comprises at least one of GaP, GaN, and GaAs extending completely through the respective source/drain region orthogonal to the current-flow direction. The at least one of the GaP, the GaN, and the GaAs of the respective source/drain region is directly against the at least one of the GaP, the GaN, and the GaAs of the channel region. Each of the source/drain regions comprises at least one of elemental silicon and metal material extending completely through the respective source/drain region orthogonal to the current-flow direction. Other embodiments are disclosed.

A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

A capacitor includes an electrode implemented in an electrode well of a substrate. The electrode well has a net N-type dopant concentration. The capacitor includes an electrode implemented in a conductive structure located above the substrate. The electrodes are separated by a dielectric layer located between the electrodes. A first tub region having a net P-type conductivity dopant concentration is located below and laterally surrounds the electrode well and a second tub region having a net N-type conductivity dopant concentration is located below and laterally surrounds the first tub region and the electrode well.

Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

A semiconductor device is provided that includes a base substrate, an insulating film on the base substrate, and an upper substrate on the insulating film. The insulating film includes a crystalline insulating material. A thickness of the insulating film is about 1 nm to about 1,000 nm, and a thickness of the upper substrate is about 1 nm to about 100 nm.

The present disclosure provides a piezoelectric sensor, a pressure detecting device, their manufacturing methods and a detection method. The piezoelectric sensor comprises a thin film transistor located on a substrate and comprising an active layer, and a piezoelectric layer that is in contact with the active layer of the thin film transistor.