A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

This application discloses a gate-all-around field effect transistor and a method for manufacturing same. In some implementations the method may include: forming a first fin structure on a substrate, where each first fin structure includes one first laminated structure, where the first laminated structure sequentially includes a sacrificial layer, a support layer, and a channel layer from bottom to top; forming a dummy gate structure across the first fin structure, where the dummy gate structure includes a dummy gate dielectric layer, a dummy gate on the dummy gate dielectric layer, and a first spacer on a side surface of the dummy gate; removing parts of the first fin structure located on two sides of the dummy gate structure, to form a second fin structure; performing first etching on a side surface of the sacrificial layer in the second fin structure, to form a first space; forming a second spacer in the first space; performing second etching on a side surface of the channel layer in the second fin structure, to form a second space; and performing selective epitaxy on the side surface of the channel layer in the second fin structure, to form a source region and a drain region, where along a direction of a channel, compared with a side surface, distal to the sacrificial layer, of the second spacer, the side surface of the channel layer after the second etching is closer to the sacrificial layer.

Embodiments of the disclosure provide a floating gate memory cell, including: a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer; a memory device, including: a control gate formed in the semiconductor layer of the SOI substrate; an insulating layer formed on the control gate; and a floating gate formed on the insulating layer; and a transistor device electrically connected to the memory device. The transistor device includes an active region formed in the semiconductor layer of the SOI substrate.

An integrated circuit structure includes a first transistor, an interconnect structure, a first dielectric layer, polycrystalline plugs, a semiconductor structure and a second transistor. The first transistor is formed on a substrate. The interconnect structure is over the first transistor. The first dielectric layer is over the interconnect structure. The polycrystalline plugs extend from a top surface of the dielectric layer into the dielectric layer. The semiconductor structure is disposed over the first dielectric layer. The second transistor is formed on the semiconductor structure.

A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.

A semiconductor device comprising a first channel region located on a substrate and a second channel region located on the substrate. A metal gate that extends across the first channel to the second channel and an air gap located in the metal gate, wherein the air gap is located between the first channel region and the second channel region, wherein the metal gate is located on top of the air gap.

Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.