An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.

In an SOI substrate having a semiconductor substrate serving as a support substrate, an insulating layer on the semiconductor substrate and a semiconductor layer on the insulating layer, an element isolation region which penetrates the semiconductor layer and the insulating layer and whose bottom part reaches the semiconductor substrate is formed, and a gate electrode is formed on the semiconductor layer via a gate insulating film. A divot is formed in the element isolation region at a position adjacent to the semiconductor layer, and a buried insulating film is formed in the divot. The gate electrode includes a part formed on the semiconductor layer via the gate insulating film, a part located on the buried insulating film and a part located on the element isolation region.

A method of fabricating a semiconductor device includes receiving a first wafer including a first substrate on a backside of the first wafer, and a first semiconductor-on-insulator (SOI) stack on a front side of the first wafer. The first SOI stack includes a first semiconductor. A second wafer is received that includes a second substrate on a backside of the second wafer, and a second SOI stack on a front side of the second wafer. The second SOI stack includes a second semiconductor. The front side of the first wafer is bonded to the front side of the second wafer, via at least one dielectric bonding material, to form a bonded wafer. The second substrate is removed. A stack of transistor devices is formed with the first semiconductor used as a first channel for a first transistor and the second semiconductor used as a second channel for a second transistor.

A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

Semiconductor devices include a semiconductor fin on a substrate. The semiconductor fin has channel region and source and drain regions. A gate stack is formed all around the channel region of the semiconductor fin, such that the channel region of the semiconductor fin is separated from the substrate. An interlayer dielectric is formed around the gate stack. At least a portion of the gate stack is formed in an undercut beneath the interlayer dielectric.

The present application discloses a semiconductor device with a contact having tapered profile and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a first region and a second region; a first gate structure positioned on the first region; and a second gate structure positioned on the second region; a first contact including a first lower portion positioned on a top surface of the first gate structure, and a first upper portion positioned on the first lower portion; and a second contact including a second lower portion positioned on a top surface of the second gate structure and a sidewall of the second gate structure, and a second upper portion positioned on the second lower portion. Sidewalls of the first lower portion are tapered and sidewalls of the second lower portion are substantially vertical.

An integrated electronic device is supported by a substrate of a silicon on insulator type. At least one transistor is formed in and on a semiconductor film of the substrate. The transistor includes a drain region and a source region of a first conductivity type and a substrate (body) region of a second conductivity type lying under a gate region. An extension region laterally continues the substrate (body) region beyond the source and drain regions and borders, in contact with, the source region through a border region having the first conductivity type. This supports formation of an electrical connection of the source region and the substrate (body) region.

This disclosure relates to forming a wrap-around contact on a nanosheet transistor, the method including: forming an etch-stop layer over a continuous outer surface of a raised source/drain (S/D) region of the nanosheet transistor; forming a sacrificial layer over the etch-stop layer, the etch-stop layer including a different material than the sacrificial layer; depositing a dielectric layer over the sacrificial layer; removing an upper portion of the dielectric layer to expose a portion of the sacrificial layer; removing the sacrificial layer selective to the etch-stop layer; and depositing a conductor in the removed upper portion of the dielectric layer to form a wrap-around contact and a second contact.

In one embodiment, an integrated circuit includes a silicon substrate, a gallium nitride (GaN) layer above the silicon substrate, a bonding layer above the GaN layer, and a silicon layer above the bonding layer. Further, the integrated circuit includes a first transistor on the GaN layer and a second transistor on the silicon layer.