A semiconductor device may include a substrate and an inverted T channel on the substrate and including a superlattice. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include source and drain regions on opposing ends of the inverted T channel, and a gate overlying the inverted T channel between the source and drain regions.

Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.

Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

A semiconductor device includes a substrate including an active pattern, a channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked, on the active pattern, a source/drain pattern connected to the plurality of semiconductor patterns, and a gate electrode including a first inner electrode provided below a first semiconductor pattern among the plurality of semiconductor patterns, on the plurality of semiconductor patterns, and a second inner electrode provided above the first semiconductor pattern, the first semiconductor pattern includes a first portion adjacent to the first inner electrode, a second portion adjacent to the second inner electrode, and a third portion between the first and second portions, the first semiconductor pattern includes a dopant having an atomic weight greater than that of silicon, and a dopant concentration of the third portion is smaller than a dopant concentration of each of the first and second portions.

In a first aspect of a present inventive subject matter, a layered structure includes a base layer, and a crystalline oxide film including a corundum structure and including an r-plane as a principal plane. The crystalline oxide film is directly arranged on the base layer or through at least one layer that is adjacently arranged to the base layer, and the crystalline oxide film is with a full width at half maximum (FWHM) of rocking curve that is 0.1 or less by -scan X-ray diffraction (XRD) measurement.

A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.

Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

A thin film transistor substrate according to an embodiment comprises: a support substrate; a bonding layer disposed on the support substrate; a thin film transistor disposed on the bonding layer, wherein the thin film transistor includes a channel layer containing a nitride-based semiconductor layer, a source electrode electrically connected to a first region of the channel layer, a drain electrode electrically connected to a second region of the channel layer, a gate electrode disposed below the channel layer, and a depletion forming layer disposed between the channel layer and the gate electrode; and a pixel electrode disposed on the thin film transistor and electrically connected to the drain electrode of the thin film transistor. The thin film transistor substrate according to the embodiment, and a display panel and a display device including the same have an advantage of implementing high resolution and reproducing a soft moving image by providing a high carrier mobility.