A display module is disclosed. The display module includes a substrate; a plurality of inorganic light-emitting diodes provided in a plurality of mounting grooves formed in the substrate, the plurality of inorganic light-emitting diodes including an inorganic light-emitting diode that has a first chip electrode and a second chip electrode; a first substrate electrode pad and a second substrate electrode pad provided at a bottom surface of a mounting groove from among the plurality of mounting grooves, the first substrate electrode pad being electrically coupled to the first chip electrode and the second substrate electrode pad being electrically coupled to the second chip electrode; and a third substrate electrode pad and a fourth substrate electrode pad provided around the mounting groove.

A display device includes a substrate including a plurality of pixels, a circuit conductive layer on the substrate, a barrier metal layer on the circuit conductive layer, a first electrode and a second electrode on the barrier metal layer and spaced apart from each other, and a light emitting element between the first electrode and the second electrode, and the barrier metal layer is electrically separated from the circuit conductive layer.

The present invention discloses a method for transferring a micro LED that is capable of easily mounting a micro LED or a nano LED on a desired position on a substrate by using an electric field.

A display device includes a first voltage line disposed on a substrate, a first power supply voltage being applied to the first voltage line, a buffer layer disposed on the first voltage line, a first transistor including a semiconductor pattern disposed on the buffer layer, a first insulating layer disposed on the semiconductor pattern of the first transistor, a first capacitor electrode disposed on the first insulating layer, a second insulating layer disposed on the first capacitor electrode, and a first electrode and a second electrode disposed on the second insulating layer and spaced apart from each other, wherein the second electrode is electrically connected to the first voltage line, and the first voltage line overlaps the first capacitor electrode in a thickness direction of the substrate.

A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.

A display device includes a substrate including a display area and a non-display area driving circuits disposed in the non-display area; first voltage wirings and second voltage wirings extending from the display area to the non-display area; and a first auxiliary wiring electrically connected to the first voltage wirings and a second auxiliary wiring electrically connected to the second voltage wirings, the first auxiliary wiring and the second auxiliary wiring being electrically connected to the driving circuit, wherein the first voltage wirings electrically connected to an odd-numbered driving circuit among the driving circuits are electrically connected to the first auxiliary wiring through a first connection wiring, and the second voltage wirings electrically connected to an even-numbered driving circuit among the driving circuits are electrically connected to the second auxiliary wiring through a second connection wiring.

A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.