A semiconductor device includes a solder supporting material above a substrate. The semiconductor device also includes a solder on the solder supporting material. The semiconductor device further includes selective laser annealed or laser ablated portions of the solder and underlying solder supporting material to form a semiconductor device having 3D features.

Embodiments include a wafer-on-wafer bonding where each wafer includes a seal ring structure around die areas defined in the wafer. Embodiments provide a further seal ring spanning the interface between the wafers. Embodiments may extend the existing seal rings of the wafers, provide an extended seal ring structure separate from the existing seal rings of the wafers, or combinations thereof.

In a light emitting device, in a bottom surface of a cavity of a Si substrate, slit-shaped through holes and through electrodes that fill the through holes are provided at a position facing a first element electrode of a light emitting element. A length of an upper surface of the through electrode in a long axis direction is larger than a height of the through electrode in a thickness direction of the Si substrate. A joining layer having a shape corresponding to a shape of the upper surface of the through electrode is disposed between the first element electrode of the light emitting element and the upper surface of the through electrode facing the first element electrode. The entire upper surface of the through electrode is joined to the first element electrode via the joining layer.

Structures and methods are disclosed for fabricating optoelectronic solid state array devices. In one case a backplane and array of micro devices is aligned and connected through bumps.

A device (2) is formed on a main surface of a semiconductor substrate (1). A passivation film (5) covers the main surface. A metallized pattern (6) is formed on the passivation film (5) and surrounds the device (2). A sealing metal layer (7) is formed on the metallized pattern (6) and includes a corner portion (10) in a planar view. A lid (8) is bonded to the metallized pattern (6) with the sealing metal layer (7) interposed therebetween and vacuum-seals the device (2). A dummy wiring (11) is softer than the metallized pattern (6), is formed at least between an outer portion of the corner portion of the sealing metal layer (7) and the semiconductor substrate (1), and does not electrically connected to the device (2).

This member connection method includes: a cutting step of forming cutting lines C in an adhesive layer at predetermined intervals at least in a width direction of an adhesive tape and making segments of the adhesive layer divided by the cutting lines C continuous at least in a lengthwise direction of the adhesive tape; a transfer step of disposing the segments to face a connection surface of one member to be connected, pressing a heating and pressing tool having an arbitrary pattern shape against the adhesive tape from a separator side and selectively transferring the segments to the one member to be connected; and a connection step for connecting another member to be connected to the one member to be connected via the segments transferred to the one member to be connected.

A package structure includes a semiconductor package, a thermal conductive gel, a thermal conductive film and a heat spreader. The thermal conductive gel is disposed over the semiconductor package. The thermal conductive film is disposed over the semiconductor package and the thermal conductive gel. A thermal conductivity of the thermal conductive film is different from a thermal conductivity of the thermal conductive gel. The thermal conductive film is surrounded by the heat spreader.

Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.

A platform for hermetic heterogeneous integration of passive and active electronic components is provided herein. The platform can include a substrate that provides a hermetic electrical interconnection between integrated circuits and passive devices, such as resistors, capacitors, and inductors. Such substrates can be formed of a dielectric, such as a ceramic, and include electrical interconnects and can further include one or more passive devices. The substrate can include one or more cavities, at least a primary cavity dimensioned to receive an active device and one or more secondary cavities can be included for secondary connector pads for interfacing with the active and passive devices and which can be separately hermetically sealed. The substrate can include a multi-coil inductor defined within alternating layers of the substrate within sidewalls that surround the primary cavity to minimize size of the device package while optimizing the size of the coil.