H01L2224/29013

METHOD OF PRODUCING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.

Semiconductor device having a cooling body with a groove

A semiconductor device includes a semiconductor module having a heat conductive portion formed of metal and also having a molded resin having a surface at which the heat conductive portion is exposed, a cooling body secured to the semiconductor module by means of bonding material, and heat conductive material formed between and thermally coupling the heat conductive portion and the cooling body.

Passive micro light-emitting diode matrix device with uniform luminance

A passive micro light-emitting diode matrix device with uniform luminance includes a micro light-emitting diode matrix including a plurality of micro light-emitting matrices, each of which includes a first layer, a plurality of light-emitting layers disposed on the first layer, a plurality of second layers disposed on the light-emitting layers, respectively, a plurality of first inner electrode layers disposed on the second layers, respectively, and a second inner electrode layer which is disposed on the first layer, and which includes a first portion and a second portion having a plurality of through holes to accommodate said light-emitting layers, respectively.

Passive micro light-emitting diode matrix device with uniform luminance

A passive micro light-emitting diode matrix device with uniform luminance includes a micro light-emitting diode matrix including a plurality of micro light-emitting matrices, each of which includes a first layer, a plurality of light-emitting layers disposed on the first layer, a plurality of second layers disposed on the light-emitting layers, respectively, a plurality of first inner electrode layers disposed on the second layers, respectively, and a second inner electrode layer which is disposed on the first layer, and which includes a first portion and a second portion having a plurality of through holes to accommodate said light-emitting layers, respectively.

Semiconductor device with a layered protection mechanism and associated systems, devices, and methods
11114415 · 2021-09-07 · ·

A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

Semiconductor device
11031324 · 2021-06-08 · ·

A semiconductor device includes a substrate, a plurality of solders, and a semiconductor chip. The plurality of solders are located adjacent to each other. At least one of composition and concentration of the plurality of solders is different from each other. The semiconductor chip includes a joining surface to be joined to the substrate with the plurality of solders. The joining surface of the semiconductor chip includes a plurality of joining areas in which heat generation of the semiconductor chip or a stress on an object to be joined is different from each other. The plurality of solders are disposed to correspond to the plurality of joining areas, respectively.

METHOD FOR PRODUCING A COMPONENT WHICH IS CONNECTED TO A SOLDER PREFORM
20210129245 · 2021-05-06 ·

A method for producing a component bonded to a solder preform, comprising the following steps: (1) providing a component having at least one contact surface, and a free solder preform, (2) producing an assembly of the component and the solder preform, which is not yet bonded to said component, by bringing a contact surface, or the sole contact surface, of the component into contact with a contact surface of the free solder preform, and (3) forming the component bonded to the solder preform by hot pressing the assembly produced in step (2) at a temperature that is 10 to 40% lower than the melting temperature of the soldering metal of the solder preform, expressed in ° C., and with a combination of pressing force and pressing duration that will effect a reduction of 10% in the original thickness of the originally free solder preform.

PACKAGE COMPRISING A SOLDER RESIST LAYER CONFIGURED AS A SEATING PLANE FOR A DEVICE

A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a semiconductor package, a thermal conductive gel, a thermal conductive film, and a heat spreader. The semiconductor package has an uneven top surface. The thermal conductive gel covers the uneven top surface of the semiconductor package. The thermal conductive film is over the uneven top surface of the semiconductor package. A thermal conductivity of the thermal conductive film is higher than a thermal conductivity of the thermal conductive gel. The heat spreader is disposed over the thermal conductive film.

Hollow sealed device and manufacturing method therefor

A ring-like sealing frame (3) and a bump (4) are simultaneously formed on a main surface of a first substrate (1) by patterning a metal paste. A ring-like protrusion (8) having a smaller width than a width of the sealing frame (3) is formed on a main surface of a second substrate (5). The main surface of the first substrate (1) and the main surface of the second substrate (5) are aligned to face each other. The sealing frame (3) is bonded to the protrusion (8), and the bump (4) is electrically bonded to the second substrate (5). A height of the protrusion (8) is 0.4 to 0.7 times a distance between the first substrate (1) and the second substrate (2) after bonding.