Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary qubit device package includes a qubit die and a package substrate, where the qubit die is coupled to the package substrate using one or more preforms. In particular, a single preform may advantageously be used to replace a plurality of individual contacts, e.g. a plurality of individual solder bumps, electrically coupling the qubit die to the package substrate. Such packages may reduce design complexity and undesired coupling, and enable inclusion of larger numbers of qubits in a single qubit die.

A semiconductor device includes a semiconductor element, a mount portion, and a sintered metal bond. The semiconductor element includes a body and an electrode pad. The body has an obverse surface facing forward in a first direction and a reverse surface facing rearward in the first direction. The electrode pad covers the element reverse surface. The mount portion supports the semiconductor element. The sintered metal bond electrically bonds the electrode pad and the mount portion. The sintered metal bond includes a first rear edge and a first front edge spaced forward in the first direction from the first rear edge. The electrode pad includes a second rear edge and a second front edge spaced forward in the first direction from the second rear edge. The first front edge of the metal bond is spaced rearward in the first direction from the second front edge of the pad.

Methods for fabricating and refurbishing an assembly are disclosed herein. The method begins by applying an adhesive layer onto a first substrate. A second substrate is placed onto the adhesive layer, thereby securing the two substrates together, the adhesive layer bounding at least one side of a channel that extends laterally between the substrates to an exterior of the assembly. And, the substrates and the adhesive layer are subjected to a bonding procedure and allowing outgassing of volatiles from the adhesive layer to escape from between the substrates through the channel, wherein the substrates bonded by the adhesive layer form a component for a semiconductor vacuum processing chamber.

The invention relates to a power module (1) comprising a substrate (2). an electrically conductive intermediate layer (3) which is arranged on the substrate (2) and which has a joining region (4) produced by means of sintering, and at least one power component (5) which is arranged on the intermediate layer (3) and the sintered joining region (4) and is connected thereto (in particular at the load connection of the power component (5)) and which has at least one connection point (6) (e.g. a control connection) connected to the intermediate layer (3), wherein the intermediate layer (3) has. in the region of the associated connection point (6). a solder region (7) produced by means of a solder preform and spaced and/or electrically insulated from the sintered joining region (4). The large active surface, which is subjected to high thermomechanical stress in the service life test. can therefore be connected via the sintered joining region (4), which ensures an especially long-lasting, reliable and resilient mechanical connection between the associated power component (5) and the substrate (2). At the associated connection point (6), e.g. the gate of a transistor, the thermomechanical stress is usually much less, which is why there in the intermediate layer (3) a solder preform can be used for producing the connection between the associated power component (5) and the substrate (2), such solder preforms being relatively cost-effectively obtainable. Furthermore. an electrical device (10) has at least one such power module (1). The joining region (4) produced by means of sintering can be formed by means of a sinter preform or by means of 3D printing. by means of a coating method or by means of screen printing/stencil printing. In the method for producing the power module (1). the intermediate layer (3) can be heated to the melting temperature of the solder if the melting temperature of the solder is higher than the sintering temperature or to the sintering temperature if the sintering temperature is higher than the melting temperature of the solder, and the layer thickness (9) of the sintering material for the joining region (4) produced by means of sintering can be larger or smaller than the layer thickness (9) of the solder for the associated solder region (7) if the sintering temperature is correspondingly lower or higher than the melting temperature of the solder. Alternatively. the melting temperature of the solder can be substantially t

Disclosed is a method of coating a conductive substrate with an adhesive, wherein the amounts and positions of conductive and non-conductive adhesives for bonding a plurality of circuit elements to the conductive substrate are set, thus preventing the spread of the adhesive from causing defects, including a poor aesthetic appearance, low electrical conductivity, and short circuits.

Disclosed is a method of coating a conductive substrate with an adhesive, wherein the amounts and positions of conductive and non-conductive adhesives for bonding a plurality of circuit elements to the conductive substrate are set, thus preventing the spread of the adhesive from causing defects, including a poor aesthetic appearance, low electrical conductivity, and short circuits.

A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates.

A method for high temperature bonding of substrates may include providing a top substrate and a bottom substrate, and positioning an insert between the substrates to form a assembly. The insert may be shaped to hold at least an amount of Sn having a low melting temperature and a gap shaped to hold at least a plurality of metal particles having a high melting temperature greater than the low melting temperature. The assembly may be heated to below the low melting temperature and held for a first period of time. The assembly may further be heated to approximately the low melting temperature and held for a period of time at a temperature equal to or greater than the low melting temperature such that the amount of Sn and the amount of metal particles form one or more intermetallic bonds. The assembly may be cooled to create a bonded assembly.

A method for high temperature bonding of substrates may include providing a top substrate and a bottom substrate, and positioning an insert between the substrates to form a assembly. The insert may be shaped to hold at least an amount of Sn having a low melting temperature and a gap shaped to hold at least a plurality of metal particles having a high melting temperature greater than the low melting temperature. The assembly may be heated to below the low melting temperature and held for a first period of time. The assembly may further be heated to approximately the low melting temperature and held for a period of time at a temperature equal to or greater than the low melting temperature such that the amount of Sn and the amount of metal particles form one or more intermetallic bonds. The assembly may be cooled to create a bonded assembly.

To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the wiring board via an adhesive layer and having a pad electrode, bonding wire connecting the pad electrode with the bonding land, and sealing body. The sealing body is, in a circuit formation region, in contact with an organic protection film and, in a scribe region and a region between the pad electrode and the scribe region, in contact with a surface protection film while not in contact with the organic protection film. A first side surface is closer to the circuit formation region side than a second one. The adhesive layer covers entirety of the semiconductor chip back surface and the second side surface of the semiconductor chip. The first side surface is in contact with the sealing body without being covered with the adhesive layer.