Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

A method for fastening a semiconductor chip on a substrate and an electronic component are disclosed. In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate. The solder metal layer may include a first metallic layer comprising an indium-tin alloy, a barrier layer arranged above the first metallic layer and a second metallic layer comprising gold arranged between the barrier layer and the semiconductor chip, wherein an amount of substance of the gold in the second metallic layer is greater than an amount of substance of tin in the first metallic layer.

A semiconductor module includes: a conductive substrate having an obverse surface and a reverse surface spaced apart in a thickness direction; a semiconductor element electrically bonded to the obverse surface and having a switching function; and a conducting member that forms a path of a main circuit current switched by the semiconductor element. The semiconductor element has a rectangular shape with four corners as viewed in the thickness direction. The conducting member includes a portion overlapping with the semiconductor element as viewed in the thickness direction. The conducting member do not overlap with at least three of the four corners of the semiconductor element.

A member includes a base material and a conductive layer. The conductive layer conducts heat or electricity. The conductive layer includes a conductive portion and a non-conductive portion. The conductive portion conducts heat or electricity. The conductive portion is disposed on at least one of an upper surface or a lower surface of the non-conductive portion and on a side surface of the non-conductive portion.

A wafer level chip scale package includes a semiconductor substrate having a first thickness, an input-output pad formed on the semiconductor substrate, a front metal layer having a second thickness formed on the input-output pad, a back metal layer having a third thickness formed on a bottom of the semiconductor substrate, and a metal bump formed on the semiconductor substrate.

The present inventive concept relates to an unfoldable layered connection comprising: a substrate; a node of connector material arranged to contact the substrate; a first extension comprising a core of connector material arranged to be in contact with the node, and flexible material arranged to at least partially enclose the core; a second extension comprising a core of connector material arranged to be in contact with the first extension via a second node of connector material, wherein the first extension is configured to be hingedly connected to the node, thereby allowing unfolding of the first extension along a z-axis being perpendicular to an extension plane of a major surface of the substrate; and wherein the second extension is hingedly connected to the second node, thereby allowing unfolding of the second extension along the z-axis, and wherein the second node is moveable along the z-axis via unfolding of the first extension.

A power semiconductor device includes an insulating substrate on which a first conductor layer is arranged on one surface, a first conductor that is connected to the first conductor layer via a first connecting material, and a semiconductor element that is connected to the first conductor via a first connecting material. When viewed from a direction perpendicular to an electrode surface of the semiconductor element, the first conductor includes a peripheral portion formed larger than the semiconductor element. A first recess is formed in the peripheral portion so that a thickness of the first connecting material becomes thicker than other portions.

An anisotropic conductive film has a three-layer structure in which a first connection layer is sandwiched between a second connection layer and a third connection layer that each are formed mainly of an insulating resin. The first connection layer has a structure in which conductive particles are arranged in a single layer in the plane direction of an insulating resin layer on a side of the second connection layer, and the thickness of the insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than that of the insulating resin layer in regions in proximity to the conductive particles.

A method of producing an anisotropic conductive film having a three-layer structure including a first connection layer, a second connection layer, and a third connection layer. The connection layers are each formed mainly of an insulating resin. The first connection layer is held between the second connection layer and the third connection layer.

Embodiments of the present disclosure include method for sequentially mounting multiple semiconductor devices onto a substrate having a composite metal structure on both the semiconductor devices and the substrate for improved process tolerance and reduced device distances without thermal interference. The mounting process causes “selective” intermixing between the metal layers on the devices and the substrate and increases the melting point of the resulting alloy materials.