A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

A semiconductor device according to embodiments includes a first base material having a first side surface, a first semiconductor chip provided above the first base material, a first insulating plate provided between the first base material and the first semiconductor chip, a first metal plate provided between the first insulating plate and the first semiconductor chip, a first bonding material provided between the first metal plate and the first semiconductor chip, the first bonding material bonding the first metal plate and the first semiconductor chip, a second bonding material provided between the first base material and the first insulating material, the second bonding material bonding the first base material and the first insulating plate, a second base material having a second side surface, a second semiconductor chip provided above the second base material, a second insulating plate provided between the second base material and the second semiconductor chip, a second metal plate provided between the second insulating plate and the second semiconductor chip, a third bonding material provided between the second metal plate and the second semiconductor chip, the third bonding material bonding the second metal plate and the second semiconductor chip, a fourth bonding material provided between the second base material and the second insulating plate, the fourth bonding material bonding the second base material and the second insulating plate, and a first base bonding portion provided between the second side surface and the first side surface and bonded to the first side surface and the second side surface.

A semiconductor device according to embodiments includes a first base material having a first side surface, a first semiconductor chip provided above the first base material, a first insulating plate provided between the first base material and the first semiconductor chip, a first metal plate provided between the first insulating plate and the first semiconductor chip, a first bonding material provided between the first metal plate and the first semiconductor chip, the first bonding material bonding the first metal plate and the first semiconductor chip, a second bonding material provided between the first base material and the first insulating material, the second bonding material bonding the first base material and the first insulating plate, a second base material having a second side surface, a second semiconductor chip provided above the second base material, a second insulating plate provided between the second base material and the second semiconductor chip, a second metal plate provided between the second insulating plate and the second semiconductor chip, a third bonding material provided between the second metal plate and the second semiconductor chip, the third bonding material bonding the second metal plate and the second semiconductor chip, a fourth bonding material provided between the second base material and the second insulating plate, the fourth bonding material bonding the second base material and the second insulating plate, and a first base bonding portion provided between the second side surface and the first side surface and bonded to the first side surface and the second side surface.

A electronic module includes a printed circuit board (PCB) substrate, a controller substrate, a controller, a memory device, and a heat spreader. The controller is disposed on the controller substrate. The memory device is disposed on the PCB substrate. The heat spreader is disposed on the controller and the memory device, in which the heat spreader has a first portion on the controller and a second portion on the memory device, and the heat spreader has a first opening between the first portion and the second portion.

A electronic module includes a printed circuit board (PCB) substrate, a controller substrate, a controller, a memory device, and a heat spreader. The controller is disposed on the controller substrate. The memory device is disposed on the PCB substrate. The heat spreader is disposed on the controller and the memory device, in which the heat spreader has a first portion on the controller and a second portion on the memory device, and the heat spreader has a first opening between the first portion and the second portion.

A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

Methods for manufacturing a display device are provided. The methods include providing a plurality of light-emitting units and a substrate. The methods also include transferring the light-emitting units to a transfer head. The methods further include attaching at least one of the plurality of light-emitting units on the transfer head to the substrate by a bonding process, wherein the transfer head and the substrate satisfy the following equation during the bonding process:
Q≤|∫.sub.T1.sup.T2A(T)dT−∫.sub.T1.sup.T3E(T)dT|<0.01, wherein A(T) is the coefficient of thermal expansion of the transfer head, E(T) is the coefficient of thermal expansion of the substrate, T1 is room temperature, T2 is the temperature of the transfer head, and T3 is the temperature of the substrate.

Methods for manufacturing a display device are provided. The methods include providing a plurality of light-emitting units and a substrate. The methods also include transferring the light-emitting units to a transfer head. The methods further include attaching at least one of the plurality of light-emitting units on the transfer head to the substrate by a bonding process, wherein the transfer head and the substrate satisfy the following equation during the bonding process:
Q≤|∫.sub.T1.sup.T2A(T)dT−∫.sub.T1.sup.T3E(T)dT|<0.01, wherein A(T) is the coefficient of thermal expansion of the transfer head, E(T) is the coefficient of thermal expansion of the substrate, T1 is room temperature, T2 is the temperature of the transfer head, and T3 is the temperature of the substrate.

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.