The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

The present disclosure provides a method of creating a bond between a first object and a second object. For example, creating a joint or die attach between a semiconductor chip and an electronic substrate, especially for harsh and high temperature environments. The method may include a step of filling a space between the first object and the second object with a filler material. Further, the method may include a step of heating the filler material to facilitate formation of a plurality of inter-diffusion layers. Accordingly, a first inter-diffusion layer may be formed between the filler material and the first object. Further, a second inter-diffusion layer may be formed between the filler material and the second object. Furthermore, in some embodiments, the first inter-diffusion layer may be contiguous with the second inter-diffusion layer. The contiguity may be facilitated by placement of at least one insert between the first object and the second object, in which the inter-diffusion of the filler material and the at least one insert may produce the third inter-diffusion layer, wherein the third inter-diffusion layer is contiguous with each of the first inter-diffusion layer and the second inter-diffusion layer.

The present disclosure provides a method of creating a bond between a first object and a second object. For example, creating a joint or die attach between a semiconductor chip and an electronic substrate, especially for harsh and high temperature environments. The method may include a step of filling a space between the first object and the second object with a filler material. Further, the method may include a step of heating the filler material to facilitate formation of a plurality of inter-diffusion layers. Accordingly, a first inter-diffusion layer may be formed between the filler material and the first object. Further, a second inter-diffusion layer may be formed between the filler material and the second object. Furthermore, in some embodiments, the first inter-diffusion layer may be contiguous with the second inter-diffusion layer. The contiguity may be facilitated by placement of at least one insert between the first object and the second object, in which the inter-diffusion of the filler material and the at least one insert may produce the third inter-diffusion layer, wherein the third inter-diffusion layer is contiguous with each of the first inter-diffusion layer and the second inter-diffusion layer.

A semiconductor device, including a substrate having an insulating plate and a conductive plate formed on the insulating plate, a semiconductor chip formed on the conductive plate, a contact part arranged on the conductive plate with a bonding member therebetween, a rod-shaped external connection terminal having a lower end portion thereof fitted into the contact part, and a lid plate having a front surface and a back surface facing the substrate. An insertion hole pierces the lid plate, forming an entrance and exit respectively on the back and front surfaces of the lid plate. The external connection terminal is inserted in the insertion hole. The semiconductor device has at least one of a guide portion with an inclined surface, fixed to a portion of the external connection terminal located in the insertion hole, or an inclined inner wall of the insertion hole.

A semiconductor device, including a substrate having an insulating plate and a conductive plate formed on the insulating plate, a semiconductor chip formed on the conductive plate, a contact part arranged on the conductive plate with a bonding member therebetween, a rod-shaped external connection terminal having a lower end portion thereof fitted into the contact part, and a lid plate having a front surface and a back surface facing the substrate. An insertion hole pierces the lid plate, forming an entrance and exit respectively on the back and front surfaces of the lid plate. The external connection terminal is inserted in the insertion hole. The semiconductor device has at least one of a guide portion with an inclined surface, fixed to a portion of the external connection terminal located in the insertion hole, or an inclined inner wall of the insertion hole.

A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.