A semiconductor structure is disclosed, including a substrate, an insulating layer on the substrate, a barrier layer on the insulating layer, a bonding dielectric layer on the barrier layer, and a bonding pad extending through the insulating layer, the barrier layer and the bonding dielectric layer. A top surface of the bonding pad exposed from the bonding dielectric layer for bonding to another bonding pad on another substrate. A liner on a bottom surface of the bonding pad directly contacts the substrate.

An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

A semiconductor device package and a method for packaging the same are provided. A semiconductor device package includes a carrier, an electronic component, a buffer layer, a reinforced structure, and an encapsulant. The electronic component is disposed over the carrier and has an active area. The buffer layer is disposed on the active area of the electronic component. The reinforced structure is disposed on the buffer layer. The encapsulant encapsulates the carrier, the electronic component and the reinforced structure.

A semiconductor device package and a method for packaging the same are provided. A semiconductor device package includes a carrier, an electronic component, a buffer layer, a reinforced structure, and an encapsulant. The electronic component is disposed over the carrier and has an active area. The buffer layer is disposed on the active area of the electronic component. The reinforced structure is disposed on the buffer layer. The encapsulant encapsulates the carrier, the electronic component and the reinforced structure.

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

A wafer structure, a method for manufacturing the same and a chip structure are provided. A first capacitor plate is arranged in a first chip, a second capacitor plate is arranged in a second chip, and the first chip is stacked together via bonding layers with the second chip with a front surface of the first chip facing toward a front surface of the second chip. In this way, a capacitor structure formed by the first capacitor plate, the second capacitor plate and dielectric materials provided therebetween is formed while bonding the first chip and second chip together, and the capacitor plate and the dielectric materials may be formed while forming a device interconnection structure in the chip, such that no additional process is required, thereby improving device integration and process integration.

A chip structure, a wafer structure and a method for manufacturing the same are provided in the present disclosure. A first chip and a second chip are bonded by bonding layers of a dielectric material. Top wiring layers are led out through bonding via holes from a back surface of a bonded chip. The bonding via holes are used for bonding and are surrounded by the bonding layers. A top wiring layer of a third chip is led out through bonding pads formed in a bonding layer. The bonding via holes are aligned with and bonded to the bonding pads to achieve bonding of the three chips. The top wiring layer of the third chip is led out from the back surface of the third chip through a lead-out pad.

The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient. The method additionally includes bonding the first and the second substrates by contacting the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate to form a substrate assembly. The method further includes post-bond annealing the assembly.

An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.