Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

The present invention achieves chemical bonding by means of a joined film made of oxides formed on a joined surface. In a vacuum container, amorphous oxide thin films are respectively formed on smooth surfaces of two substrates, and the two substrates overlap such that the amorphous oxide thin films formed on the two substrates come into contact with each other, thereby causing chemical bonding involving an atomic diffusion at a joined interface between the amorphous oxide thin films to join the two substrates.

A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes first semiconductor dies spaced apart from one another, second semiconductor dies stacked upon the first semiconductor dies with a one-to-one correspondence and electrically coupled to the first semiconductor dies, a first composite structure laterally interposed between two first semiconductor dies, a second composite structure laterally interposed between two second semiconductor dies, and a support substrate bonded to the second semiconductor dies and the second composite structure. The first composite structure includes a first material layer adjoining sidewalls of the two first semiconductor dies and a second material layer connected to and different from the first material layer. The second composite structure includes a third material layer adjoining sidewalls of the two second semiconductor dies and a fourth material layer connected to and different from the third material layer.

There is provided an imaging device, an electronic apparatus including an imaging device, and an automotive vehicle including an electronic apparatus including an imaging device, including: a first substrate including a first set of photoelectric conversion units; a second substrate including a second set of photoelectric conversion units; and an insulating layer between the first substrate and the second substrate; where the insulating layer has a capability to reflect a first wavelength range of light and transmit a second wavelength range of light that is longer than the first wavelength range of light.

Interposer-less multi-chip module are provided. In one aspect, an interposer-less multi-chip module includes: a substrate; a base film disposed on the substrate; and chips pressed into the base film, wherein top surfaces of the chips are coplanar. For instance, the chips can have varying thicknesses and are pressed into the base film to different depths such that top surfaces of the chips are coplanar. An interconnect layer having back-end-of line (BEOL) metal wiring can be present on the wafer over the chips. Methods of forming an interposer-less multi-chip module are also provided.

A semiconductor light emitting device includes: a light emitting element assembly including a semiconductor light emitting element including a support substrate and a light emitting semiconductor layer provided on the support substrate, and a light guide member adhered to the semiconductor light emitting element by an adhesive layer; and a first coating film formed of an inorganic material, which is a light reflector configured to cover a side surface of the light emitting element assembly.

A light emitting module including a circuit board and a lighting emitting device thereon and including first, second, and third LED stacks each including first and second conductivity type semiconductor layers, a first bonding layer between the second and third LED stacks, a second bonding layer between the first and second LED stacks, a first planarization layer between the second bonding layer and the third LED stack, a second planarization layer on the first LED stack, a lower conductive material extending along sides of the first planarization layer, the second LED stack, the first bonding layer, and electrically connected to the first conductivity type semiconductor layers of each LED stack, respectively, and an upper conductive material between the circuit board and the lower conductive material, in which a width of an upper end of the upper conductive material is greater than a width of the corresponding upper conductive material.

A light emitting module including a circuit board and a lighting emitting device thereon and including first, second, and third LED stacks each including first and second conductivity type semiconductor layers, a first bonding layer between the second and third LED stacks, a second bonding layer between the first and second LED stacks, a first planarization layer between the second bonding layer and the third LED stack, a second planarization layer on the first LED stack, a lower conductive material extending along sides of the first planarization layer, the second LED stack, the first bonding layer, and electrically connected to the first conductivity type semiconductor layers of each LED stack, respectively, and an upper conductive material between the circuit board and the lower conductive material, in which a width of an upper end of the upper conductive material is greater than a width of the corresponding upper conductive material.

A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.