A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.

A method for forming a chip package is provided. The method includes forming a plurality of conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive ti structures surround the semiconductor die. The method further includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Structures and formation methods of chip packages are provided. The method includes disposing a semiconductor die over a carrier substrate. The method also includes disposing an interposer substrate over the carrier substrate. The interposer substrate has a recess that penetrates through opposite surfaces of the interposer substrate. The interposer substrate has interior sidewalls surrounding the semiconductor die, and the semiconductor die is as high as or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure over the interposer substrate.

An anisotropic conductive film has first and second connection layers formed on a first layer surface. The first connection layer is a photopolymerized resin layer, and the second is thermo- or photo-cationically, anionically, or radically polymerizable resin layer. On the surface of the first connection layer on a second connection layer side, conductive particles for anisotropic conductive connection are in a single layer. The first connection layer has fine projections and recesses in a surface. An anisotropic conductive film of another aspect has first, second, and third connection layers layered in sequence. The first layer formed of photo-radically polymerized resin. The second and third layers are formed of thermo-cationically or thermo-anionically polymerizable resin, photo-cationically or photo-anionically polymerizable resin, thermo-radically polymerizable resin, or photo-radically polymerizable resin. On a surface of the first connection layer on a second connection layer side, conductive particles for anisotropic conductive connection are in a single layer.

Structures and formation methods of chip packages are provided. The method includes disposing a semiconductor die over a carrier substrate. The method also includes disposing an interposer substrate over the carrier substrate. The interposer substrate has a recess that penetrates through opposite surfaces of the interposer substrate. The interposer substrate has interior sidewalls surrounding the semiconductor die, and the semiconductor die is as high as or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure over the interposer substrate.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.

Thermally conductive adhesive materials having a first metallic component with a high melting point metal; a second metallic component having a low melting point metal; a fatty acid, an optional amine, an optional triglyceride and optional additives. Also provided are methods of making the same and uses thereof for adhering electronic components to substrates.

Provided is an electroconductive adhesive with which, when made into an electroconductive adhesive and sintered suitably at low temperature even without pressurization during sintering of the electroconductive adhesive, a sintered body having high denseness and mechanical strength (shear strength) is formed. An electroconductive adhesive containing silver particles A having an average particle size of less than 40 nm, silver particles B having an average particle size in the range of 40 nm to less than 500 nm, silver particles C having an average particle size in the range of 0.5 to less than 5.5 μm, and a solvent, wherein the mass ratio of silver particles A:silver particles B:silver particles C is 1-20:30-60:40-70.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.