A bonding structure formed on a substrate includes an indium layer and a passivating nickel plating formed on the indium layer. The nickel plating serves to prevent a reaction involving the indium layer.

A power electronics module includes a substrate with a substrate metallization layer, which is separated into conducting areas for providing conducting paths for the power electronics module; a semiconductor switch chip bonded with a first power electrode to a first conducting area of the substrate metallization layer; a conductor plate bonded to a second power electrode of the semiconductor switch chip opposite to the first power electrode.

Methods for bonding substrates used, for example, in substrate-level packaging, are provided herein. In some embodiments, a method for bonding substrates includes: performing electrochemical deposition (ECD) to deposit at least one material on each of a first substrate and a second substrate, performing chemical mechanical polishing (CMP) on the first substrate and the second substrate to form a bonding interface on each of the first substrate and the second substrate, positioning the first substrate on the second substrate so that the bonding interface on the first substrate aligns with the bonding interface on the second substrate, and bonding the first substrate to the second substrate using the bonding interface on the first substrate and the bonding interface on the second substrate.

A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. Light from the micro multi-color LED device is emitted horizontally from each of the LED structures and reflected upward via some reflective structures. In some embodiments, each LED structure is connected to a pixel driver and/or a common electrode. The LED structures are bonded together through bonding layers. In some embodiments, planarization layers enclose each of the LED structures or the micro multi-color LED device. In some embodiments, one or more of reflective layers, refractive layers, micro-lenses, spacers, and reflective cup structures are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness.

A hybrid bonding layer includes a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, and a ball grid array (BGA) disposed within the MIO layer. The MIO layer and the BGA may be disposed between a pair of bonding layers. The MIO layer and the BGA each have a melting point above a TLP sintering temperature and the pair of bonding layers each have a melting point below the TLP sintering temperature such that the hybrid bonding layer can be transient liquid phase bonded between a substrate and a semiconductor device. The pair of bonding layers may include a first pair of bonding layers with a melting point above the TLP sintering temperature and a second pair of bonding layers with a melting point below the TLP sintering temperature.

A hybrid bonding layer includes a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, and a ball grid array (BGA) disposed within the MIO layer. The MIO layer and the BGA may be disposed between a pair of bonding layers. The MIO layer and the BGA each have a melting point above a TLP sintering temperature and the pair of bonding layers each have a melting point below the TLP sintering temperature such that the hybrid bonding layer can be transient liquid phase bonded between a substrate and a semiconductor device. The pair of bonding layers may include a first pair of bonding layers with a melting point above the TLP sintering temperature and a second pair of bonding layers with a melting point below the TLP sintering temperature.

A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. Light from the micro multi-color LED device is emitted horizontally from each of the LED structures and reflected upward via some reflective structures. In some embodiments, each LED structure is connected to a pixel driver and/or a common electrode. The LED structures are bonded together through bonding layers. In some embodiments, planarization layers enclose each of the LED structures or the micro multi-color LED device. In some embodiments, one or more of reflective layers, refractive layers, micro-lenses, spacers, and reflective cup structures are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness.

A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. Light from the micro multi-color LED device is emitted substantially vertically upward through each of the LED structures. In some embodiments, each LED structure is connected to a pixel driver and/or a common electrode. The LED structures are bonded together through bonding layers. In some embodiments, planarization layers enclose each of the LED structures or the micro multi-color LED device. In some embodiments, one or more of reflective layers, refractive layers, micro-lenses, spacers, and reflective cup structures are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness.

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

A chip bonding film is provided and includes an adhesive film layer that is curable by heat, and fillers that are thermally conductive and are contained in the adhesive film layer, each of the fillers including magnetic particles, wherein a heat dissipation path is formed by the fillers in a vertical direction from a lower surface to an upper surface of the adhesive film layer.