Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use a film during fabrication to control the distribution of an under-fill material between one or more components and a packaging substrate. The method includes mounting components to a first side of a packaging substrate and applying a film to a second side of a packaging substrate. The method also includes mounting a lower component to the second side of the packaging substrate and under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent. The method also includes removing the film on the second side of the packaging substrate and mounting solder balls to the second side of the packaging substrate after removal of the film.

A semiconductor device in which occurrence of peeling between a filling member and a metal terminal is suppressed is obtained. The semiconductor device includes: an insulating substrate having a front surface and a back surface, and having a semiconductor element joined to the front surface; a base plate joined to the back surface of insulating substrate; a case member surrounding insulating substrate; a filling member having an upper surface, covering insulating substrate, and filling a region surrounded by base plate and case member; and a metal member having a plate shape that leans toward an upper surface side of filling member inside filling member, has one end joined to the front surface of insulating substrate and another end separated from an inner wall of case member, and is exposed from the upper surface of filling member.

A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.

A semiconductor package includes a substrate, a first chip on the substrate, a second chip on the substrate and arranged side-by-side with the first chip, and a support structure on the second chip. A width of the support structure is equal to or greater than a width of the second chip.

A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Embodiments of the present application provide the chip packaging structure, the chip module and the electronic terminal. In the chip packaging structure, the chip is accommodated in the trench of the substrate to decrease the thickness and volume of the chip packaging structure; and the plastic package is provided on the surface of the substrate on which the chip is disposed to plastically package the chip, which not only ensures the structural strength of the chip packaging structure, but also reduces the warpage that may be caused due to the decrease of the thickness of the chip packaging structure as much as possible. In addition, the surface of the plastic package is treated to be a flat surface, such that the chip module has good flatness and the adaptability of the chip module is improved.

An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.

A semiconductor package includes a redistribution substrate having a first side and an opposite second side, a semiconductor chip on the first side of the redistribution substrate, a silicon capacitor on the second side of the redistribution substrate, a plurality of solder balls on the second side of the redistribution substrate and adjacent the silicon capacitor, and a metal pattern in the redistribution substrate and positioned between the silicon capacitor and the solder balls. The metal pattern includes a first portion extending in a first direction, and a second portion connected to the first portion and extending in a second direction different from the first direction.

A semiconductor device, including a first conductive portion including a first conducting region and a first wiring region communicating with the first conducting region via a first communicating portion, a second conductive portion including a second conducting region and a second wiring region that communicates with the second conducting region via a second communicating portion and that faces the first wiring region with a prescribed space therebetween, and a wiring member electrically connecting the first wiring region and the second wiring region in a wiring direction. The first communicating portion and the second communicating portion are separate from each other when viewed from the wiring direction.