Inner leads having die pads having upper surfaces to which semiconductor elements are mounted each have a stepped profile, and surfaces of portions of the inner leads are exposed from a sealing resin in plan view. Outer leads connected to the inner leads have first bends at side surfaces of the sealing resin to extend in a direction on a side of the upper surfaces of the die pads, so that a miniaturized semiconductor device can be obtained.

Inner leads having die pads having upper surfaces to which semiconductor elements are mounted each have a stepped profile, and surfaces of portions of the inner leads are exposed from a sealing resin in plan view. Outer leads connected to the inner leads have first bends at side surfaces of the sealing resin to extend in a direction on a side of the upper surfaces of the die pads, so that a miniaturized semiconductor device can be obtained.

Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.

Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.

A semiconductor package includes a lead frame having a die paddle and a plurality of leads including a gate lead spaced apart from the die paddle. The semiconductor package further includes a semiconductor die attached to the die paddle and having a plurality of pads including a gate pad, a plurality of electrical conductors connecting the pads to the leads, an encapsulant encasing the semiconductor die and a portion of the leads such that part of the leads are not covered by the encapsulant, and a ferrite material embedded in the encapsulant and surrounding a portion of the electrical conductor that connects the gate pad to the gate lead. A method of manufacturing the semiconductor package and a semiconductor module with integrated ferrite material are also provided.

A light-emitting device in which the emission intensity of light-emitting elements is improved by making heat generated by light emission of the light-emitting elements be effectively released is provided. The light-emitting device includes a mounting substrate including a mounting region, light-emitting elements mounted on the mounting region, a sealing resin which contains a phosphor and integrally seals the light-emitting elements, and at least one heat transfer member which is arranged among the light-emitting elements on the mounting region, is embedded in the sealing resin, and has a higher thermal conductivity than the sealing resin.

A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.

Provided is a semiconductor device capable of having simple wiring in mounting the semiconductor device. The semiconductor device includes at least one P-terminal, at least one N-terminal, a power output terminal, at least one power supply terminal, at least one ground (GND) terminal, at least one control terminal, and a package that is rectangular in a plan view and accommodates an insulated gate bipolar transistor (IGBT) being a high-side switching element, an IGBT being a low-side switching element, and a control circuit. The at least one control terminal is disposed on a first side of the package, opposite to a second side on which the power output terminal is disposed. The at least one P-terminal, the at least one N-terminal, the at least one power supply terminal, and the at least one GND terminal are disposed on a third side of the package, orthogonal to the second side.

A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.

A semiconductor module includes: semiconductor arrangements each including a first switching element having a first emitter terminal and a first collector terminal, a second switching element having a second emitter terminal and a second collector terminal, a first diode element having a first anode terminal and a first cathode terminal, and a second diode element having a second anode terminal and a second cathode terminal. A first conductor rail is electrically coupled to the first anode terminals and first emitter terminals. A second conductor rail is electrically coupled to the second anode terminals and the second emitter terminals. A third conductor rail is electrically coupled to the first anode terminals and first emitter terminals. A fourth conductor rail is electrically coupled to the second anode terminals and the second emitter terminals.