Patent classifications
H01L2224/48155
SEMICONDUCTOR POWER MODULE AND POWER CONVERSION APPARATUS
A semiconductor power module in which a three-phase AC inverter is incorporated in a package includes first to third circuit patterns on which second, fourth, and sixth switching elements are mounted, respectively, and a fourth circuit pattern on which first, third, and fifth switching elements are mounted; a second main electrode to which all of main electrode wirings of the second, fourth, and sixth switching elements are connected; a second main electrode terminal connected to the second main electrode; a first main electrode electrically connected to the fourth circuit pattern; and a first main electrode terminal connected to the first main electrode, and each of the main electrode wirings of the second, fourth, and sixth switching elements is provided so that a main electrode wiring closer to the second main electrode terminal in a horizontal direction in plan view has a longer length.
SEMICONDUCTOR PACKAGING STRUCTURE AND PACKAGE HAVING STRESS RELEASE STRUCTURE
A semiconductor packaging structure includes a copper heat-sink with a shim projection which provides a stress release structure. The heat-sink with the shim projection may be used in conjunction with a pedestal in order to further reduce the thermal stress produced from the mismatch of thermal properties between the copper heat-sink metal and the ceramic frame. The copper heat-sink with a shim projection may also be part of the semiconductor package along with a lead frame, the ceramic frame, a semiconductor device, a capacitor, a wire bond and a ceramic lid or an encapsulation. The copper heat-sink, the ceramic frame and the lead frame are all chosen to be cost effective, and chosen such that the packaging process for the semiconductor device is able to achieve a smaller size while maintaining high reliability, low cost, and suitability for volume manufacturing.
SEMICONDUCTOR APPARATUS, POWER MODULE, AND MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS
A semiconductor apparatus includes: a first conductor plate; a second conductor plate separated from the first conductor plate; a plurality of semiconductor devices having back surface electrodes connected to the first conductor plate; a relay substrate mounted on the second conductor plate and including a plurality of first relay pads and a second relay pad connected to the plurality of first relay pads; a plurality of metal wires respectively connecting control electrodes of the plurality of semiconductor devices to the plurality of first relay pads; a first conductor block connected to front surface electrodes of the plurality of semiconductor devices; a second conductor block connected to the second relay pad; and a sealing material sealing the first and second conductor plates, the plurality of semiconductor devices, the relay substrate, the metal wire, and the first and second conductor blocks, the sealing material includes a first principal surface and a second principal surface opposed to each other, the first conductor plate is exposed from the first principal surface, the second conductor plate is not exposed from the first principal surface, and the first and second conductor blocks are exposed from the second principal surface.
SEMICONDUCTOR DEVICE
A semiconductor device, including a circuit pattern, a contact part and an external connection terminal. The contact part has a cylindrical through-hole and first and second opening ends opposite to each other, the second opening end being joined to the circuit pattern. The external connection terminal has a prismatic main body portion and first and second end portions, the second end portion being inserted into the through-hole from the first opening end of the contact part. The main body portion of the external connection terminal has an insertion prevented portion formed thereon. The contact part includes an insertion preventing portion formed on an inner circumferential surface of the through-hole, the insertion preventing portion being so positioned as to be substantially downstream, with respect to an insertion direction of the external connection terminal, from the main body portion of the external connection terminal inserted into the through-hole.
SEMICONDUCTOR PACKAGE INCLUDING HEAT RADIATION STRUCTURE, COOLING SYSTEM APPLYING THE SEMICONDUCTOR PACKAGE, SUBSTRATE INCLUDING HEAT RADIATION STRUCTURE AND METHOD OF MANUFACTURING THE SUBSTRATE
Provided is a semiconductor package including a heat radiation structure, a cooling system applying the semiconductor package, a substrate including a heat radiation structure, and a method of manufacturing the substrate, and more particularly, a semiconductor package including a heat radiation structure, a cooling system applying the semiconductor package, a substrate including a heat radiation structure, and a method of manufacturing the substrate, in which an area contacting a coolant enlarges through heat radiating posts having various forms and structures and a coolant flow path is formed by post holes so that heat generated from semiconductor chips may be efficiently cooled.
SEMICONDUCTOR MODULE, POWER SEMICONDUCTOR MODULE, AND POWER ELECTRONIC EQUIPMENT USING THE SEMICONDUCTOR MODULE OR THE POWER SEMICONDUCTOR MODULE
The semiconductor module includes: a heat dissipation board including first to third wiring patterns; a first metal plate on the first wiring pattern, a second metal plate on the second wiring pattern, a first semiconductor chip and a first intermediate board which are on the first metal plate, a second semiconductor chip and a second intermediate board which are on the second metal plate. A first metal film on the first intermediate board is electrically connected to the first semiconductor chip and the second metal plate, and a second metal film on the second intermediate board is electrically connected to the second semiconductor chip and the third wiring pattern.
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer.
Packaging Structure and Power Amplifier
A packaging structure and a power amplifier, the packaging structure including a first component, a second component, a printed circuit board, and a metal plate having an etched pattern. The printed circuit board is disposed on the metal plate, and the printed circuit board has an open slot. The first component is disposed in the open slot, and the first component is disposed on the metal plate. The first component is connected to the printed circuit board, the second component is disposed on the printed circuit board, and the second component is connected to the printed circuit board.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING POWER CONTROL CIRCUIT
In a method for manufacturing a semiconductor device, a back surface of each of plurality of current-carrying semiconductor elements each having a plurality of P-N junction diodes built-in is connected to a first principal surface of a conductor plate. Further, a conductor piece is connected to a front surface of each of the plurality of current-carrying semiconductor elements. Then, a current-carrying test is conducted on the plurality of P-N junction diodes with a second principal surface of the conductor plate exposed on a bottom surface of an intermediate product of a semiconductor device including the plurality of current-carrying semiconductor elements, the conductor plate, and the conductor piece.
Power electronics module
A power electronics module includes a substrate with a substrate metallization layer, which is separated into conducting areas for providing conducting paths for the power electronics module; a semiconductor switch chip bonded with a first power electrode to a first conducting area of the substrate metallization layer; a conductor plate bonded to a second power electrode of the semiconductor switch chip opposite to the first power electrode.