The present disclosure relates to a power module comprising: a base plate; a ceramic substrate bonded to the top surface of the base plate; a semiconductor chip bonded to the top surface of the ceramic substrate; a spacer bonded to the top surface of the ceramic substrate so as to be spaced apart from the semiconductor chip; a connection pin provided at an electrode layer formed on the top surface of the spacer; and a bonding wire for connecting a terminal of the semiconductor chip to the electrode layer of the spacer.

A semiconductor device includes first and second conductive parts, a first bonding wire connecting the first and second conductive parts and having a non-flat portion between opposite ends thereof so that a portion between the opposite ends is away from the first and second conductive parts, a case having a housing space to accommodate the first and second conductive parts, including a sidewall having first to fourth lateral faces surrounding the housing space to form a rectangular shape in a plan view, and a cover disposed on the sidewall, a sealing member filling the case to seal the first bonding wire, and a first stress relaxer for relieving a stress in the first bonding wire. The first bonding wire extends from the second lateral face toward the fourth lateral face, and the first stress relaxer is positioned between the first bonding wire and the first lateral face.

Provided is a method of processing a NAND flash memory device including at least one NAND flash memory and a memory controller configured to control the at least one NAND flash memory. The method includes etching a portion of a first substrate of the NAND flash memory device to expose a wire connecting the at least one NAND flash memory and the memory controller to each other, dividing the wire into a first wire and a second wire by etching a first area of the etched first substrate, and connecting, to a second substrate, the first wire to which the at least one NAND flash memory is connected.

A semiconductor module includes a sealing body including a terminal portion electrically connected to a semiconductor element and an insulating resin that seals the semiconductor element, a case that houses the sealing body, and a conductive member provided in the case and including a contact portion that has contact with the terminal portion of the sealing body. The terminal portion is exposed from the insulating resin. The case includes a holding member attaching portion capable of attaching a holding member used in combination with the case and holds the sealing body in a state where the terminal portion of the sealing body has contact with the contact portion of the conductive member. The holding member attaching portion is configured so that a pressing load is applied to a contact surface of the contact portion contacting the terminal portion when the holding member is attached.

The object is to provide a technology for enabling reduction of adhesion of a bonding material to a particular electrode. A semiconductor device includes: a semiconductor element with a surface including a first electrode and a second electrode; a protective film formed on the surface of the semiconductor element and having insulating properties, the protective film exposing the first electrode and the second electrode; a metal lead electrode bonded to the first electrode exposed from the protective film; and a bonding material with which the first electrode exposed from the protective film is bonded to the metal lead electrode. The metal lead electrode includes an abutment portion being a protrusion abutting the protective film and blocking between the bonding material and the second electrode in a cross-sectional view.

Provided is a heat sink having a clad structure of CoMo composite materials and Cu materials, satisfying high heat-sink properties required of the heat sink for use in a semiconductor package with a frame on which a high-output and small-sized semiconductor is mounted, and preventing, when applied to the semiconductor package with a frame, crack of the frame due to local stress concentration. The heat sink has three or more Cu layers and two or more CuMo composite layers alternately stacked in a thickness direction so that the Cu layers are outermost layers on both sides thereof, the Cu layers as the outermost layers each having a thickness t.sub.1 of 40 m or more, the heat sink satisfying 0.06t.sub.1/T0.27 (where T: heat sink thickness) and t.sub.2/T0.36/[(total number of layers1)/2] (where t.sub.2: CuMo composite layer thickness, the total number of layers: sum of numbers of Cu layers and CuMo composite layers).

A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

Power semiconductor packages described herein each include a substrate having two or more metal layers and one or more insulating layers for separating the metal layers. The substrate insulating layers are formed from a polymer material to reduce the CTE mismatch between the substrate metal layers and the substrate insulating layers.

A fingerprint sensing chip packaging method and package are provided. The method includes: providing a cover plate, providing a fingerprint sensing chip, where a fingerprint sensing region and contact pads at periphery of the region are arranged on a front surface of the chip, electrically connecting the contact pads to a back surface of the chip, forming a first conductive structure electrically connected to the contact pads on the back surface of the chip, laminating the front surface of the chip with a back surface of the cover plate, providing a flexible printed circuit, where a second conductive structure is arranged on a back surface of the circuit and an opening is arranged in the circuit, laminating a front surface of the circuit with the back surface of the cover plate, and electrically connecting the first conductive structure to the second conductive structure.

A semiconductor module arrangement includes a substrate including a dielectric insulation layer and a first metallization layer arranged on a surface of the dielectric insulation layer, wherein the first metallization layer comprises a first section, a second section, and a third section, and a first semiconductor body and an identical second semiconductor body arranged on the first metallization layer, wherein each of the first semiconductor body and the second semiconductor body has a first contact pad, a second contact pad, and a third contact pad arranged on a top side of the respective semiconductor body that faces away from the substrate, wherein the third contact pad of the first semiconductor body is electrically coupled to the third section of the first metallization layer by means of a first electrical connection element, the third contact pad of the second semiconductor body is electrically coupled to the third section of the first metallization layer by means of a second electrical connection element, the semiconductor module arrangement further includes at least one third terminal element arranged on the third section, a first current path between the third contact pad of the first semiconductor body and the at least one third terminal element provides identical voltage and current transfer characteristics as a second current path between the third contact pad of the second semiconductor body and the at least one third terminal element, and each of the first and second electrical connection elements includes one or more bonding wires, one or more bonding ribbons, a connection rail, or a section of an additional metallization layer of the substrate that is contacted by corresponding vias.