A packaged electronic device includes a die pad directly connected to a first set of conductive leads of a leadframe structure, a semiconductor die attached to the conductive die pad, a conductive support structure directly connected to a second set of conductive leads, and spaced apart from all other conductive structures of the leadframe structure. A magnetic assembly is attached to the conductive support structure, and a molded package structure that encloses the conductive die pad, the conductive support structure, the semiconductor die, the magnetic assembly and portions of the conductive leads, the molded package structure including a top side, and an opposite bottom side, wherein the lamination structure is centered between the top and bottom sides.

A semiconductor device forming a bidirectional switch includes first and second carriers, first and second semiconductor chips arranged on the first and second carriers, respectively, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor chips. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

A semiconductor module includes: an insulation layer; a semiconductor element that includes a main electrode and is mounted on the insulation layer; a wiring member that is electrically connected to the main electrode of the semiconductor element; a first resin that encases the semiconductor element and the wiring member; and a second resin that covers a part of the wiring member. A thermal decomposition temperature or a melting point of the second resin is greater than a maximum of guaranteed operating temperature of the semiconductor element and is less than a thermal decomposition temperature or a melting point of the first resin.

A power semiconductor module includes an insulating substrate, a first conductive circuit pattern, a second conductive circuit pattern, a first semiconductor device, a second semiconductor device, a sealing member, and a first barrier layer. The sealing member seals the first semiconductor device, the second semiconductor device, the first conductive circuit pattern, and the second conductive circuit pattern. At least one of the first barrier layer and the sealing member includes a first stress relaxation portion. This configuration improves the reliability of the power semiconductor module.

Various embodiments relate to a packaged radio frequency (RF) amplifier device implementing a split bondwire where the direct ground connection of an output capacitor is replaced with a set of bondwires connecting to ground in a direction opposite to the wires connecting to the output of a transistor to an output pad. This is done in order to reduce the effects of mutual inductance between the various bondwires associated with the output of the RF amplifier device.

A power converter package includes a leadframe including first and second die pads, and supports connected to first leads, and second leads. A first semiconductor die including first bond pads is on the first die pad, and a second semiconductor die including second bond pads is on the second die pad. A transformer stack includes a top magnetic sheet and a bottom magnetic sheet on respective sides of a laminate substrate that includes a coil within, and coil contacts. A silicon block is attached to the bottom magnetic sheet and edges of the laminate substrate are attached to the supports. Bond wires are between the first bond pads and the second leads, the second bond pads and the second leads, and the first and second bond pads and the coil contacts. Mold encapsulates the respective semiconductor and the transformer stack. A bottom of the silicon block is exposed from the mold.

According to an aspect of the present disclosure, a semiconductor device includes a substrate, a resin case surrounding a region just above the substrate in a planar view, a semiconductor chip provided in the region and an electrode including a first portion pulled out from an upper surface of the resin case and a second portion provided below the upper surface of the resin case and to be inserted into the resin case, and being electrically connected to the semiconductor chip, wherein a first notch is formed over the first portion to the second portion in the electrode, and a first groove is formed to expose a portion, formed in the second portion, in the first notch on the upper surface of the resin case.

A semiconductor device includes a substrate, a conductive section, a sealing resin, and a conductive section wire. The substrate includes a substrate obverse face and a substrate reverse face oriented in opposite directions to each other in a thickness direction. The conductive section is formed of a conductive material and located on the substrate obverse face. The conductive section includes a first section and a second section spaced apart from each other. The sealing resin covers at least a part of the substrate and an entirety of the conductive section. The conductive section wire is conductively bonded to the first section and the second section of the conductive section.

A semiconductor device according to the present disclosure includes: a lead frame having a plurality of die pad portions electrically independent from each other; a power semiconductor element provided on each of the die pad portions; a wire electrically connecting the power semiconductor element and the lead frame; an epoxy-based resin provided on at least a part of the lead frame; and a sealing resin covering at least each of the die pad portions, the power semiconductor element, the wire, and the epoxy-based resin.

According to an embodiment, provided is a semiconductor device includes an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip provided on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer. The second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit.