A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.

A power module and a manufacturing method includes a chip; an upper substrate provided above the chip and formed with a circuit pattern; a lower substrate provided below the chip and formed with a circuit pattern; and a spacer including a plurality of metal portions electrically connecting at least two among the chip, the upper substrate and the lower substrate to transmit an electrical signal, and an insulating portion positioned between the plurality of metal portions and insulating the metal portions.

The present disclosure relates to a ring-frame power package that includes a thermal carrier, a spacer ring residing on the thermal carrier, and a ring structure residing on the spacer ring. The ring structure includes a ring body and a number of interconnect tabs that protrude from an outer periphery of the ring body. Herein, a portion of the carrier surface of the thermal carrier is exposed through an interior opening of the spacer ring and an interior opening of the ring body. The spacer ring is not electronically conductive and prevents the interconnect tabs from electrically coupling to the thermal carrier. Each interconnect tab includes a top plated area and a bottom plated area, which is electrically coupled to the top plated area.

A semiconductor assembly includes a power semiconductor, a housing containing the power semiconductor, and electrically conductive channels. The electrically conductive channels are arranged to direct coolant through the housing. Heat generated by the power semiconductor can therefore be absorbed by the coolant. The electrically conductive channels are also electrically connected with the power semiconductor to form terminals for the power semiconductor.

An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

An electronic device has a fuse circuit including a semiconductor die and first and second bond wires, the semiconductor die having a bond pad and a fuse, the fuse having first and second portions, the bond pad coupled to the first portion of the fuse, and the second portion of the fuse coupled to a protected circuit, the first bond wire having a first end coupled to the bond pad and a second end coupled to a conductive terminal, and the second bond wire having a first end coupled to the second end of the first bond wire and a second end coupled to the conductive terminal.

Example embodiments relate to electronic packages and electronic devices that include the same. One embodiment includes an electronic package. The electronic package includes a package body. The electronic package also includes a heat-conducting substrate arranged inside the package body and having a bottom surface that is exposed to an outside of the package body. Additionally, the electronic package includes an electronic circuit arranged inside the package body and including a semiconductor die that has a bottom surface with which it is mounted to the heat-conducting substrate and an opposing upper surface. Further, the electronic package includes one or more leads partially extending from outside the package body to inside the package body and over the minimum bounding box, each lead having a first end that is arranged inside the package body. In addition, the electronic package includes one or more bondwires for connecting the first end(s) to the electronic circuit.

Heat from a semiconductor device is effectively dissipated while the height of the semiconductor device is kept low. A semiconductor device includes a cooler configured to cool a semiconductor module. The semiconductor module includes: a metal block, a semiconductor element, a terminal connected to the semiconductor element, and a resin covering a part of the terminal, the metal block, and the semiconductor element. The cooler includes: a metal base including the semiconductor module in a plan view while being in contact with a lower surface of the semiconductor module, and a cooling pipe disposed on an upper surface of the metal base and configured to cool the semiconductor module. The cooling pipe at least partially surrounds the semiconductor module in a plan view.

[Problem] An object of the present invention is to miniaturize and integrate plural power semiconductors in an electronic circuit in a low cost without occurrence of a problem of a heat dissipation or the like.

[Means for solving the problem] The present invention is a power semiconductor module that comprises plural arrangements of power semiconductor elements comprising a power semiconductor bare chip which one electrode portion thereof is connected to a metal plate which at least one external connecting terminal is formed and other external connecting terminals which are electrically connected to other electrode portions of the power semiconductor bare chip, and that are contained in a same package, comprises wherein the power semiconductor elements are basically same outline, electrodes of the bare chip of the power semiconductor elements are mutually connected between the power semiconductor elements with a metal connector or a wiring, and the package is a resin mold package that seals the power semiconductor elements with an electrical insulating resin.

A semiconductor device includes a semiconductor element, a die pad, an encapsulating member, and a plurality of leads. The die pad has a front surface on which the semiconductor element is mounted. The encapsulating member covers and seals the semiconductor element. The plurality of leads each have a first end connected to the semiconductor element in an inside of the encapsulating member and a second end led out from a side surface of the encapsulating member. A lower surface of a package including the semiconductor element, the die pad, and the encapsulating member is located on a back surface side of the die pad and has a convexly curved shape.