A semiconductor device includes an insulating substrate and an upper inductor that is formed on the insulating substrate and is a component of a transformer that performs contactless communication between different potentials. Here, the upper inductor is configured to be applied with a first potential. The upper inductor is formed so as to be magnetically coupled to a lower inductor that is configured to be applied with a second potential different from the first potential.

A semiconductor device includes a semiconductor chip including a substrate, a transistor provided on an upper surface of the substrate and having an input electrode to which a high frequency signal is input, an output electrode from which the high frequency signal is output, and a reference potential electrode to which a reference potential is supplied, and a metal pattern provided on the upper surface of the substrate and electrically connected to the reference potential electrode, a first capacitor including a first lower electrode provided on the metal pattern and electrically connected to the metal pattern, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer, and a first bonding wire electrically connecting the first upper electrode and a first electrode which is any one of the input electrode and the output electrode.

A method for encasing an electrical unit includes connecting the electrical unit to a leadframe and encasing the electrical unit with a first plastic material to form an inner molded body, so that a plurality of contacts of the electrical unit project from the inner molded body. The inner molded body is punched out of the lead frame. The method also includes connecting at least one first contact and one second contact to a shunt resistor. The inner molded body is encased with a second plastic material to form an outer molded body.

A semiconductor device includes: a base material having a first terminal; a semiconductor chip having a first electrode pad electrically connected with the first terminal, a second electrode pad to which a power supply potential is to be supplied, and a third electrode pad to which a reference potential is to be supplied, and mounted on the base material via a first member; a chip capacitor having a first electrode and a second electrode, and mounted on the semiconductor chip via a second member; a first wire electrically connecting the first electrode pad with the first terminal; a second wire electrically connecting the second electrode pad with the first electrode without going through the base material; and a third wire electrically connecting the third electrode pad with the second electrode without going through the base material.

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180 (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.

Systems and methods are disclosed herein for a low cost, compact size, and thin half-etched leadframe quad-flat no-leads (QFN) package that integrates RF passive elements in the QFN leadframe for linearized PA design and RF FEMs. The integrated RF passive elements in the QFN leadframe may include RF inductors (e.g., meanders lines or spirals) for amplifier bias or RF matching, extension bar of the ground paddle for inter-stage matching or jumper pads for connection. The integrated RF passive elements may also include transmission lines for output power matching, coupled line structures such as RF couplers, RF divider or combiner realized using transmission lines with proper impedance and length, jumper pads for adjusting the bond wire length, etc. The RF parameters of the integrated passive elements are adjustable using different length and number of wire bond for fine tuning the performance of the PAM or the RF FEM.

A packaged semiconductor device includes a lead frame and a semiconductor die. The semiconductor die has first and second opposing sides, and the first side of the die is mounted to the lead frame. A first set of bond wires and/or bump bonds are configured to electrically couple the die to the lead frame. A passive circuit element is on a substrate, and the substrate is mounted to the second side of the die. A second set of bond wires and/or bump bonds are configured to electrically couple the passive circuit element to the die. A molding material is configured to encapsulate the passive circuit element, the die, and at least a portion of the lead frame.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, rows of terminal leads disposed around the die pad; a surface mount device (SMD) mounted and bonded with a bond wire in the semiconductor package; and a molding compound encapsulating the semiconductor die and the SMD, the bond wire, and at least partially encapsulating the die pad and the terminal leads. The SMD may be mounted in the semiconductor package by using a non-conductive paste or a conductive paste. The die pad, the tie bars and the terminal leads are coplanar.

A battery pack includes a battery protection circuit module package coupled with a holder. The protection circuit module includes a basic package including a lead frame having a plurality of leads spaced apart from each other, and protection circuit elements provided on the lead frame, and an encapsulant and a holder simultaneously produced by disposing the basic package in a first injection mold and injecting a resin melt into the first injection mold to perform an insert injection molding process. The encapsulant encapsulates the protection circuit elements to expose parts of the lead frame, wherein the encapsulant and the basic package configure the battery protection circuit module package, and wherein the holder is coupled to the battery protection circuit module package due to the insert injection molding process.

A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.